Origen-SDK / origen_verilog / 56

Builds Branch Commit Type Ran Committer Via Coverage
56 master Fix for port names starting with input_ push ginty travis-ci pending completion   set done
55 master Added test case for reported parse issue push ginty travis-ci pending completion   set done
54 v0.5.0 Updated app version and history push ginty travis-ci pending completion   set done
53 master Updated app version and history push ginty travis-ci pending completion   set done
51 master Don't evaluate all Verilog, only as required push ginty travis-ci pending completion   set done
50 v0.4.0 Updated app version and history push ginty travis-ci pending completion   set done
49 master Updated app version and history push ginty travis-ci pending completion   set done
48 master Recorded new version in the version tracker push ginty travis-ci pending completion   set done
47 master Update README.md push web-flow travis-ci pending completion   set done
46 master Merge pull request #9 from Origen-SDK/fixes Fixes push web-flow travis-ci pending completion   set done
45 master Fix for #8 and added runtime defines Pull #9 web-flow travis-ci pending completion   set done
44 fixes Fix for #8 and added runtime defines push ginty travis-ci pending completion   set done
43 fixes Fixed line numbers in parse error msg when ifdefs are present push ginty travis-ci pending completion   set done
42 fixes Fix for #5 and #7 push ginty travis-ci pending completion   set done
41 fixes Fix for #2 and #6 push ginty travis-ci pending completion   set done