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469 of 492 relevant lines covered (95.33%)
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| Builds | Branch | Commit | Type | Ran | Committer | Via | Coverage |
|---|---|---|---|---|---|---|---|
| 30 | master | spec: add ABS and IND load opcodes | push | travis-ci | pending completion | ||
| 29 | master | spec: note that alu32 ops use only the lower 32 bits of operands | push | travis-ci | pending completion | ||
| 28 | master | vm: remove checks duplicated by the validator | push | travis-ci | pending completion | ||
| 27 | master | vm: fix lddw with high bit on low word set | push | travis-ci | pending completion | ||
| 26 | master | vm: zero ubpf_vm | push | travis-ci | pending completion | ||
| 25 | master | vm: add exit check in validate() | push | travis-ci | pending completion | ||
| 24 | master | jit: runtime checks for division by zero | push | travis-ci | pending completion | ||
| 23 | master | jit: factor out mul/div/mod code generation | push | travis-ci | pending completion | ||
| 22 | master | vm: fix bswap32 | push | travis-ci | pending completion | ||
| 21 | master | vm: implement shifting by a register The shift amount has to come from cl. | push | travis-ci | pending completion |