ravenrd / DRAMPower
87%
master: 88%

LAST BUILD BRANCH: iterable_counters
DEFAULT BRANCH: master
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LAST BUILD ON BRANCH refact_ca
branch: refact_ca
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120

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Merge branch 'master' into refact_ca

5 of 5 new or added lines in 3 files covered. (100.0%)

1559 of 1789 relevant lines covered (87.14%)

245908.19 hits per line

Relevant lines Covered
1789 RELEVANT LINES 1559 COVERED LINES
245908.19 HITS PER LINE
Source Files on refact_ca
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
120 refact_ca Merge branch 'master' into refact_ca push Sv3n travis-ci pending completion  
119 refact_ca Disabled warning prints for now. push Sv3n travis-ci pending completion  
118 refact_ca Removed (some of the?) >0 guards that would always evaluate to 0. For all memspecs we ship with DRAMPower, RCD > XP, and RP > XP. push Sv3n travis-ci pending completion  
115 refact_ca Annotated zero_guard functions with warning prints. push Sv3n travis-ci pending completion  
114 refact_ca [#41] Use zero_guard() instead of max(zero, ...). Reduces the complexity if the code, removing common subexpressions. push Sv3n travis-ci pending completion  
113 refact_ca Formatted statements to be on one line. We can handle more than 80 columns per line, right? :) push Sv3n travis-ci pending completion  
112 refact_ca [#41] In small scopes, abbreviate memTimingSpec. push Sv3n travis-ci pending completion  
111 refact_ca [#41] Added MS_NOT_IN_PD state for the memory. push Sv3n travis-ci pending completion  
110 refact_ca [#41] Removed useless if-statement. push Sv3n travis-ci pending completion  
106 refact_ca [#41] Indent cleanup, added helper variable for readability. push Sv3n travis-ci pending completion  
See All Builds (112)