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lsils / mockturtle
80%
master: 83%

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LAST BUILD BRANCH: common
DEFAULT BRANCH: master
Repo Added 10 Apr 2020 02:52PM UTC
Token xMxkGLf1fgN0im5wChgAAPH5POKID0vT1 regen
Build 416 Last
Files 133
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add9c26523c44f712ecabcb747c4a0f5d8ca2d18-PR-319

Pull #319

github

GitHub
Merge 0aad5e066 into c3f6ab45f
Pull Request #319: Access module and I/O names through Verilog reader

73 of 73 new or added lines in 1 file covered. (100.0%)

7567 of 9516 relevant lines covered (79.52%)

94597.34 hits per line

Relevant lines Covered
Build:
Build:
9516 RELEVANT LINES 7567 COVERED LINES
94597.34 HITS PER LINE
Source Files on msoeken/verilog
  • List 0
  • Changed 14
  • Source Changed 1
  • Coverage Changed 14
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

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Builds Branch Commit Type Ran Committer Via Coverage
add9c265... msoeken/verilog Merge 0aad5e066 into c3f6ab45f Pull #319 11 Apr 2020 03:21PM UTC GitHub github pending completion  
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