Nic30 / hdlConvertor
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master: 60%

LAST BUILD BRANCH: mesonbuild
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LAST BUILD ON BRANCH replace_Verilog2001_with_sv2017
branch: replace_Verilog2001_with_sv2017
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rm verbose from coveralls-lcov, outputs is beyolond the travis limit

30711 of 52897 relevant lines covered (58.06%)

9263.7 hits per line

Relevant lines Covered
52897 RELEVANT LINES 30711 COVERED LINES
9263.7 HITS PER LINE
Source Files on replace_Verilog2001_with_sv2017
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

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590 replace_Verilog2001_with_sv2017 rm verbose from coveralls-lcov, outputs is beyolond the travis limit push Nic30 travis-ci pending completion  
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