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Nic30 / hdlConvertor
58%
master: 60%

Build:
Build:
LAST BUILD BRANCH: mesonbuild
DEFAULT BRANCH: master
Repo Added 08 Sep 2019 10:32AM UTC
Files 335
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LAST BUILD ON BRANCH replace_Verilog2001_with_sv2017
branch: replace_Verilog2001_with_sv2017
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  • replace_Verilog2001_with_sv2017
  • HEAD
  • master
  • mesonbuild
  • sv2017
  • v1.3
  • v1.4
  • v1.5
  • v1.9
  • v2.0
  • v2.1
  • verilog_pp_line_directive

pending completion
590

push

travis-ci

Nic30
rm verbose from coveralls-lcov, outputs is beyolond the travis limit

30711 of 52897 relevant lines covered (58.06%)

9263.7 hits per line

Relevant lines Covered
Build:
Build:
52897 RELEVANT LINES 30711 COVERED LINES
9263.7 HITS PER LINE
Source Files on replace_Verilog2001_with_sv2017
  • List 0
  • Changed 0
  • Source Changed 0
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
590 replace_Verilog2001_with_sv2017 rm verbose from coveralls-lcov, outputs is beyolond the travis limit push 10 Oct 2019 04:45PM UTC Nic30 travis-ci pending completion  
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  • Repo on GitHub
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