29150059569

Committed 11 Jul 2026 10:52AM UTC coverage: 95.56% (+0.03%) from 95.53%

Build # 29150059569

Build Type

push

github

Committed by

henrythasler

Commit Message

add f32 support for call instruction

Co-authored-by: Copilot <copilot@github.com>

Coverage Stats

23 of 23 new or added lines in 2 files covered. (100.0%)

2 existing lines in 2 files now uncovered.

2303 of 2410 relevant lines covered (95.56%)

66.77 hits per line

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98.41

/src/assembler/aarch64/fp_processing.rs

use super::*;

/// Generates the AArch64 instruction for moving a floating-point value between registers.
///
/// Uses `fmov` (general) to move between floating-point registers and general-purpose registers.
/// Uses `fmov` (register) to move between floating-point registers.
///
/// `FMOV <rd>, <rn>`
pub fn fmov(rd: Reg, rn: Reg, size_rn: RegSize) -> u32 {
    match (rd, rn) {
        (Reg::IReg(rd), Reg::FReg(rn)) => {
            select_float_instr(0x1E260000, 0x9E660000, size_rn) | (rn & 0x1F) << 5 | rd & 0x1F
        }
        (Reg::FReg(rd), Reg::IReg(rn)) => {
            select_float_instr(0x1E270000, 0x9E670000, size_rn) | (rn & 0x1F) << 5 | rd & 0x1F
        }
        (Reg::FReg(rd), Reg::FReg(rn)) => {
            select_float_instr(0x1E204000, 0x1E604000, size_rn) | (rn & 0x1F) << 5 | rd & 0x1F
        }
        _ => panic!("Invalid register types for fmov"),
    }
}

pub fn fadd_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {
    let instr = select_float_instr(0x1E202800, 0x1E602800, size);
    instr | (rm & 0x1F) << 16 | (rn & 0x1F) << 5 | rd & 0x1F
}

pub fn fsub_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {
    let instr = select_float_instr(0x1E203800, 0x1E603800, size);
    instr | (rm & 0x1F) << 16 | (rn & 0x1F) << 5 | rd & 0x1F
}

pub fn fmul_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {
    let instr = select_float_instr(0x1E200800, 0x1E600800, size);
    instr | (rm & 0x1F) << 16 | (rn & 0x1F) << 5 | rd & 0x1F
}

pub fn fdiv_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {
    let instr = select_float_instr(0x1E201800, 0x1E601800, size);
    instr | (rm & 0x1F) << 16 | (rn & 0x1F) << 5 | rd & 0x1F
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_fmov() {
        // fmov x0, d1
        assert_eq!(
            fmov(
                Reg::IReg(IReg::X0),
                Reg::FReg(FReg::D1),
                RegSize::Float64bit
            ),
            0x9E660020
        );
    }

    #[test]
    fn test_fadd_scalar() {
        // fadd s10, s13, s17
        assert_eq!(
            fadd_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),
            0x1E3129AA
        );
        // fadd d1, d3, d7
        assert_eq!(
            fadd_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),
            0x1E672861
        );
    }

    #[test]
    fn test_fsub_scalar() {
        // fsub s10, s13, s17
        assert_eq!(
            fsub_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),
            0x1E3139AA
        );
        // fsub d1, d3, d7
        assert_eq!(
            fsub_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),
            0x1E673861
        );
    }

    #[test]
    fn test_fmul_scalar() {
        // fmul s10, s13, s17
        assert_eq!(
            fmul_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),
            0x1E3109AA
        );
        // fmul d1, d3, d7
        assert_eq!(
            fmul_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),
            0x1E670861
        );
    }

    #[test]
    fn test_fdiv_scalar() {
        // fdiv s10, s13, s17
        assert_eq!(
            fdiv_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),
            0x1E3119AA
        );
        // fdiv d1, d3, d7
        assert_eq!(
            fdiv_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),
            0x1E671861
        );
    }

    #[test]
    #[should_panic]
    fn test_fadd_scalar_panic() {
        fadd_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Int32bit);
    }

    #[test]
    #[should_panic]
    fn test_fmov_panic() {
        fmov(Reg::IReg(IReg::X0), Reg::FReg(FReg::D1), RegSize::Int32bit);
    }
}

1	use super::*;
2
3	/// Generates the AArch64 instruction for moving a floating-point value between registers.
4	///
5	/// Uses `fmov` (general) to move between floating-point registers and general-purpose registers.
6	/// Uses `fmov` (register) to move between floating-point registers.
7	///
8	/// `FMOV <rd>, <rn>`
9	pub fn fmov(rd: Reg, rn: Reg, size_rn: RegSize) -> u32 {	38✔
10	match (rd, rn) {	38✔
11	(Reg::IReg(rd), Reg::FReg(rn)) => {	30✔
12	select_float_instr(0x1E260000, 0x9E660000, size_rn) \| (rn & 0x1F) << 5 \| rd & 0x1F	30✔
13	}
14	(Reg::FReg(rd), Reg::IReg(rn)) => {	6✔
15	select_float_instr(0x1E270000, 0x9E670000, size_rn) \| (rn & 0x1F) << 5 \| rd & 0x1F	6✔
16	}
17	(Reg::FReg(rd), Reg::FReg(rn)) => {	2✔
18	select_float_instr(0x1E204000, 0x1E604000, size_rn) \| (rn & 0x1F) << 5 \| rd & 0x1F	2✔
19	}
UNCOV 20	_ => panic!("Invalid register types for fmov"),	×
21	}
22	}	38✔
23
24	pub fn fadd_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {	7✔
25	let instr = select_float_instr(0x1E202800, 0x1E602800, size);	7✔
26	instr \| (rm & 0x1F) << 16 \| (rn & 0x1F) << 5 \| rd & 0x1F	7✔
27	}	7✔
28
29	pub fn fsub_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {	6✔
30	let instr = select_float_instr(0x1E203800, 0x1E603800, size);	6✔
31	instr \| (rm & 0x1F) << 16 \| (rn & 0x1F) << 5 \| rd & 0x1F	6✔
32	}	6✔
33
34	pub fn fmul_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {	8✔
35	let instr = select_float_instr(0x1E200800, 0x1E600800, size);	8✔
36	instr \| (rm & 0x1F) << 16 \| (rn & 0x1F) << 5 \| rd & 0x1F	8✔
37	}	8✔
38
39	pub fn fdiv_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {	6✔
40	let instr = select_float_instr(0x1E201800, 0x1E601800, size);	6✔
41	instr \| (rm & 0x1F) << 16 \| (rn & 0x1F) << 5 \| rd & 0x1F	6✔
42	}	6✔
43
44	#[cfg(test)]
45	mod tests {
46	use super::*;
47
48	#[test]
49	fn test_fmov() {	1✔
50	// fmov x0, d1
51	assert_eq!(	1✔
52	fmov(	1✔
53	Reg::IReg(IReg::X0),	1✔
54	Reg::FReg(FReg::D1),	1✔
55	RegSize::Float64bit	1✔
56	),
57	0x9E660020
58	);
59	}	1✔
60
61	#[test]
62	fn test_fadd_scalar() {	1✔
63	// fadd s10, s13, s17
64	assert_eq!(	1✔
65	fadd_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),	1✔
66	0x1E3129AA
67	);
68	// fadd d1, d3, d7
69	assert_eq!(	1✔
70	fadd_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),	1✔
71	0x1E672861
72	);
73	}	1✔
74
75	#[test]
76	fn test_fsub_scalar() {	1✔
77	// fsub s10, s13, s17
78	assert_eq!(	1✔
79	fsub_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),	1✔
80	0x1E3139AA
81	);
82	// fsub d1, d3, d7
83	assert_eq!(	1✔
84	fsub_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),	1✔
85	0x1E673861
86	);
87	}	1✔
88
89	#[test]
90	fn test_fmul_scalar() {	1✔
91	// fmul s10, s13, s17
92	assert_eq!(	1✔
93	fmul_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),	1✔
94	0x1E3109AA
95	);
96	// fmul d1, d3, d7
97	assert_eq!(	1✔
98	fmul_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),	1✔
99	0x1E670861
100	);
101	}	1✔
102
103	#[test]
104	fn test_fdiv_scalar() {	1✔
105	// fdiv s10, s13, s17
106	assert_eq!(	1✔
107	fdiv_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),	1✔
108	0x1E3119AA
109	);
110	// fdiv d1, d3, d7
111	assert_eq!(	1✔
112	fdiv_scalar(FReg::D1, FReg::D3, FReg::D7, RegSize::Float64bit),	1✔
113	0x1E671861
114	);
115	}	1✔
116
117	#[test]
118	#[should_panic]
119	fn test_fadd_scalar_panic() {	1✔
120	fadd_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Int32bit);	1✔
121	}	1✔
122
123	#[test]
124	#[should_panic]
125	fn test_fmov_panic() {	1✔
126	fmov(Reg::IReg(IReg::X0), Reg::FReg(FReg::D1), RegSize::Int32bit);	1✔
127	}	1✔
128	}

henrythasler / rust-tiny-wasm / 29150059569

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