27492556297

Committed 14 Jun 2026 07:57AM UTC coverage: 92.969% (-1.2%) from 94.121%

Build # 27492556297

Build Type

Pull #6

github

Committed by

web-flow

Commit Message

Merge b6c98ccdf into df49d44a8

Pull Request Pull Request #6: Feature/floats

Coverage Stats

533 of 584 new or added lines in 19 files covered. (91.27%)

5 existing lines in 3 files now uncovered.

2023 of 2176 relevant lines covered (92.97%)

62.72 hits per line

Source File
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86.21

/src/assembler/aarch64/fp_processing.rs

use super::*;

pub fn fmov(rd: Reg, rn: Reg, size_rn: RegSize) -> u32 {
    match (rd, rn) {
        (Reg::IReg(rd), Reg::FReg(rn)) => match size_rn {
            RegSize::Float32bit => 0x1E260000 | (rn & 0x1F) << 5 | rd & 0x1F,
            RegSize::Float64bit => 0x9E660000 | (rn & 0x1F) << 5 | rd & 0x1F,
            _ => panic!("Invalid register sizes for fmov"),
        },
        (Reg::FReg(rd), Reg::IReg(rn)) => match size_rn {
            RegSize::Float32bit => 0x1E270000 | (rn & 0x1F) << 5 | rd & 0x1F,
            RegSize::Float64bit => 0x9E670000 | (rn & 0x1F) << 5 | rd & 0x1F,
            _ => panic!("Invalid register sizes for fmov"),
        },
        _ => panic!("Invalid register types for fmov"),
    }
}

pub fn fadd_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {
    match size {
        RegSize::Float32bit => 0x1E202800 | (rm & 0x1F) << 16 | (rn & 0x1F) << 5 | rd & 0x1F,
        RegSize::Float64bit => 0x1E602800 | (rm & 0x1F) << 16 | (rn & 0x1F) << 5 | rd & 0x1F,
        _ => panic!("Invalid register sizes for fadd"),
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_fmov() {
        // fmov x0, d1
        assert_eq!(
            fmov(
                Reg::IReg(IReg::X0),
                Reg::FReg(FReg::D1),
                RegSize::Float64bit
            ),
            0x9E660020
        );
    }

    #[test]
    fn test_fadd_scalar() {
        // fadd s10, s13, s17
        assert_eq!(
            fadd_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),
            0x1E3129AA
        );
    }
}

1	use super::*;
2
3	pub fn fmov(rd: Reg, rn: Reg, size_rn: RegSize) -> u32 {	13✔
4	match (rd, rn) {	13✔
5	(Reg::IReg(rd), Reg::FReg(rn)) => match size_rn {	9✔
6	RegSize::Float32bit => 0x1E260000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	4✔
7	RegSize::Float64bit => 0x9E660000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	5✔
NEW 8	_ => panic!("Invalid register sizes for fmov"),	×
9	},
10	(Reg::FReg(rd), Reg::IReg(rn)) => match size_rn {	4✔
11	RegSize::Float32bit => 0x1E270000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	2✔
12	RegSize::Float64bit => 0x9E670000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	2✔
NEW 13	_ => panic!("Invalid register sizes for fmov"),	×
14	},
NEW 15	_ => panic!("Invalid register types for fmov"),	×
16	}
17	}	13✔
18
19	pub fn fadd_scalar(rd: FReg, rn: FReg, rm: FReg, size: RegSize) -> u32 {	5✔
20	match size {	5✔
21	RegSize::Float32bit => 0x1E202800 \| (rm & 0x1F) << 16 \| (rn & 0x1F) << 5 \| rd & 0x1F,	3✔
22	RegSize::Float64bit => 0x1E602800 \| (rm & 0x1F) << 16 \| (rn & 0x1F) << 5 \| rd & 0x1F,	2✔
NEW 23	_ => panic!("Invalid register sizes for fadd"),	×
24	}
25	}	5✔
26
27	#[cfg(test)]
28	mod tests {
29	use super::*;
30
31	#[test]
32	fn test_fmov() {	1✔
33	// fmov x0, d1
34	assert_eq!(	1✔
35	fmov(	1✔
36	Reg::IReg(IReg::X0),	1✔
37	Reg::FReg(FReg::D1),	1✔
38	RegSize::Float64bit	1✔
39	),
40	0x9E660020
41	);
42	}	1✔
43
44	#[test]
45	fn test_fadd_scalar() {	1✔
46	// fadd s10, s13, s17
47	assert_eq!(	1✔
48	fadd_scalar(FReg::S10, FReg::S13, FReg::S17, RegSize::Float32bit),	1✔
49	0x1E3129AA
50	);
51	}	1✔
52	}

henrythasler / rust-tiny-wasm / 27492556297

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