27089938512

Committed 07 Jun 2026 10:29AM UTC coverage: 92.847% (-1.3%) from 94.121%

Build # 27089938512

Build Type

Pull #6

github

Committed by

web-flow

Commit Message

Merge 0a4fe7baf into df49d44a8

Pull Request Pull Request #6: Feature/floats

Coverage Stats

426 of 470 new or added lines in 17 files covered. (90.64%)

5 existing lines in 3 files now uncovered.

1921 of 2069 relevant lines covered (92.85%)

64.65 hits per line

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94.74

/src/assembler/aarch64/processing.rs

use super::*;

pub fn mov_reg(rd: IReg, rm: IReg, size: RegSize) -> u32 {
    bit::orr_reg(rd, IReg::XZR, rm, Shift::Lsl, 0, size)
}

pub fn mov_sp(rd: IReg, rn: IReg, size: RegSize) -> u32 {
    arithmetic::add_imm(rd, rn, 0, false, size)
}

pub fn mov_imm(rd: IReg, imm16: u32, size: RegSize) -> u32 {
    movz(rd, imm16, 0, size)
}

pub fn movn(rd: IReg, imm16: u32, shift: u32, size: RegSize) -> u32 {
    let mut instr = select_instr(0x12800000, 0x92800000, size);
    instr |= ((shift >> 4) & 0x3) << 21; // hw field (0-3 for 64-bit, 0-1 for 32-bit)
    instr |= (imm16 & 0xFFFF) << 5; // imm16 field
    instr |= rd & 0x1F; // Rd (destination register)
    instr
}

pub fn movz(rd: IReg, imm16: u32, shift: u32, size: RegSize) -> u32 {
    let mut instr = select_instr(0x52800000, 0xD2800000, size);
    instr |= ((shift >> 4) & 0x3) << 21; // hw field (0-3 for 64-bit, 0-1 for 32-bit)
    instr |= (imm16 & 0xFFFF) << 5; // imm16 field
    instr |= rd & 0x1F; // Rd (destination register)
    instr
}

pub fn movk(rd: IReg, imm16: u32, shift: u32, size: RegSize) -> u32 {
    let mut instr = select_instr(0x72800000, 0xF2800000, size);
    instr |= ((shift >> 4) & 0x3) << 21; // hw field (0-3 for 64-bit, 0-1 for 32-bit)
    instr |= (imm16 & 0xFFFF) << 5; // imm16 field
    instr |= rd & 0x1F; // Rd (destination register)
    instr
}

pub fn fmov(rd: Reg, rn: Reg, size_rn: RegSize) -> u32 {
    match (rd, rn) {
        (Reg::IReg(rd), Reg::FReg(rn)) => match size_rn {
            RegSize::Float32bit => 0x1E260000 | (rn & 0x1F) << 5 | rd & 0x1F,
            RegSize::Float64bit => 0x9E660000 | (rn & 0x1F) << 5 | rd & 0x1F,
            _ => panic!("Invalid register sizes for fmov"),
        },
        (Reg::FReg(rd), Reg::IReg(rn)) => match size_rn {
            RegSize::Float32bit => 0x1E270000 | (rn & 0x1F) << 5 | rd & 0x1F,
            RegSize::Float64bit => 0x9E670000 | (rn & 0x1F) << 5 | rd & 0x1F,
            _ => panic!("Invalid register sizes for fmov"),
        },
        _ => panic!("Invalid register types for fmov"),
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_mov_reg() {
        // mov x10, x11
        assert_eq!(mov_reg(IReg::X10, IReg::X11, RegSize::Reg64bit), 0xAA0B03EA);
    }

    #[test]
    fn test_movz() {
        // MOVZ X3, #0x1234, LSL #16
        assert_eq!(movz(IReg::X3, 0x1234, 16, RegSize::Reg64bit), 0xD2A24683);
        // MOVZ X7, 0xABCD, LSL #48
        assert_eq!(movz(IReg::X7, 0xabcd, 48, RegSize::Reg64bit), 0xD2F579A7);
        // MOV X8, #0xdef0
        assert_eq!(mov_imm(IReg::X8, 0xdef0, RegSize::Reg64bit), 0xD29BDE08);
    }

    #[test]
    fn test_movk() {
        // MOVK X15, #0xffff, LSL #32
        assert_eq!(movk(IReg::X15, 0xffff, 32, RegSize::Reg64bit), 0xF2DFFFEF);
        // MOVK W0, #0x80, LSL #16
        assert_eq!(movk(IReg::W0, 0x80, 16, RegSize::Reg32bit), 0x72A01000);
        //   EXPECT_THROW(encode_movk(X15, 0xFFFF, 32, reg_size_t::SIZE_8BIT), std::runtime_error);
    }

    #[test]
    fn test_movn() {
        // movn x11, #0x10, lsl #32
        assert_eq!(movn(IReg::X11, 0x10, 32, RegSize::Reg64bit), 0x92C0020B);
    }
}

1	use super::*;
2
3	pub fn mov_reg(rd: IReg, rm: IReg, size: RegSize) -> u32 {	159✔
4	bit::orr_reg(rd, IReg::XZR, rm, Shift::Lsl, 0, size)	159✔
5	}	159✔
6
7	pub fn mov_sp(rd: IReg, rn: IReg, size: RegSize) -> u32 {	158✔
8	arithmetic::add_imm(rd, rn, 0, false, size)	158✔
9	}	158✔
10
11	pub fn mov_imm(rd: IReg, imm16: u32, size: RegSize) -> u32 {	213✔
12	movz(rd, imm16, 0, size)	213✔
13	}	213✔
14
15	pub fn movn(rd: IReg, imm16: u32, shift: u32, size: RegSize) -> u32 {	40✔
16	let mut instr = select_instr(0x12800000, 0x92800000, size);	40✔
17	instr \|= ((shift >> 4) & 0x3) << 21; // hw field (0-3 for 64-bit, 0-1 for 32-bit)	40✔
18	instr \|= (imm16 & 0xFFFF) << 5; // imm16 field	40✔
19	instr \|= rd & 0x1F; // Rd (destination register)	40✔
20	instr	40✔
21	}	40✔
22
23	pub fn movz(rd: IReg, imm16: u32, shift: u32, size: RegSize) -> u32 {	452✔
24	let mut instr = select_instr(0x52800000, 0xD2800000, size);	452✔
25	instr \|= ((shift >> 4) & 0x3) << 21; // hw field (0-3 for 64-bit, 0-1 for 32-bit)	452✔
26	instr \|= (imm16 & 0xFFFF) << 5; // imm16 field	452✔
27	instr \|= rd & 0x1F; // Rd (destination register)	452✔
28	instr	452✔
29	}	452✔
30
31	pub fn movk(rd: IReg, imm16: u32, shift: u32, size: RegSize) -> u32 {	55✔
32	let mut instr = select_instr(0x72800000, 0xF2800000, size);	55✔
33	instr \|= ((shift >> 4) & 0x3) << 21; // hw field (0-3 for 64-bit, 0-1 for 32-bit)	55✔
34	instr \|= (imm16 & 0xFFFF) << 5; // imm16 field	55✔
35	instr \|= rd & 0x1F; // Rd (destination register)	55✔
36	instr	55✔
37	}	55✔
38
39	pub fn fmov(rd: Reg, rn: Reg, size_rn: RegSize) -> u32 {	8✔
40	match (rd, rn) {	8✔
41	(Reg::IReg(rd), Reg::FReg(rn)) => match size_rn {	4✔
42	RegSize::Float32bit => 0x1E260000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	2✔
43	RegSize::Float64bit => 0x9E660000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	2✔
NEW 44	_ => panic!("Invalid register sizes for fmov"),	×
45	},
46	(Reg::FReg(rd), Reg::IReg(rn)) => match size_rn {	4✔
47	RegSize::Float32bit => 0x1E270000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	2✔
48	RegSize::Float64bit => 0x9E670000 \| (rn & 0x1F) << 5 \| rd & 0x1F,	2✔
NEW 49	_ => panic!("Invalid register sizes for fmov"),	×
50	},
NEW 51	_ => panic!("Invalid register types for fmov"),	×
52	}
53	}	8✔
54
55	#[cfg(test)]
56	mod tests {
57	use super::*;
58
59	#[test]
60	fn test_mov_reg() {	1✔
61	// mov x10, x11
62	assert_eq!(mov_reg(IReg::X10, IReg::X11, RegSize::Reg64bit), 0xAA0B03EA);	1✔
63	}	1✔
64
65	#[test]
66	fn test_movz() {	1✔
67	// MOVZ X3, #0x1234, LSL #16
68	assert_eq!(movz(IReg::X3, 0x1234, 16, RegSize::Reg64bit), 0xD2A24683);	1✔
69	// MOVZ X7, 0xABCD, LSL #48
70	assert_eq!(movz(IReg::X7, 0xabcd, 48, RegSize::Reg64bit), 0xD2F579A7);	1✔
71	// MOV X8, #0xdef0
72	assert_eq!(mov_imm(IReg::X8, 0xdef0, RegSize::Reg64bit), 0xD29BDE08);	1✔
73	}	1✔
74
75	#[test]
76	fn test_movk() {	1✔
77	// MOVK X15, #0xffff, LSL #32
78	assert_eq!(movk(IReg::X15, 0xffff, 32, RegSize::Reg64bit), 0xF2DFFFEF);	1✔
79	// MOVK W0, #0x80, LSL #16
80	assert_eq!(movk(IReg::W0, 0x80, 16, RegSize::Reg32bit), 0x72A01000);	1✔
81	// EXPECT_THROW(encode_movk(X15, 0xFFFF, 32, reg_size_t::SIZE_8BIT), std::runtime_error);
82	}	1✔
83
84	#[test]
85	fn test_movn() {	1✔
86	// movn x11, #0x10, lsl #32
87	assert_eq!(movn(IReg::X11, 0x10, 32, RegSize::Reg64bit), 0x92C0020B);	1✔
88	}	1✔
89	}

henrythasler / rust-tiny-wasm / 27089938512

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