18638570188

Committed 20 Oct 2025 12:38AM UTC coverage: 20.202% (-0.01%) from 20.213%

Build # 18638570188

Build Type

Pull #308

github

Committed by

web-flow

Commit Message

Merge 73a1640e9 into 416357998

Pull Request Pull Request #308: Add tests for PciSegment

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1163 existing lines in 25 files now uncovered.

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/alioth/src/pci/bus.rs

// Copyright 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

use std::sync::Arc;
use std::sync::atomic::{AtomicU32, Ordering};

use bitfield::bitfield;

use crate::mem;
use crate::mem::emulated::{Action, Mmio};
#[cfg(target_arch = "x86_64")]
use crate::pci::host_bridge::HostBridge;
use crate::pci::segment::PciSegment;
use crate::pci::{Bdf, PciDevice, Result};

bitfield! {
    #[derive(Copy, Clone, Default)]
    struct Address(u32);
    impl Debug;
    enabled, _: 31;
    bus, _: 23, 16;
    dev, _: 15, 11;
    func, _: 10, 8;
    offset, _: 7, 0;
}

impl Address {
    pub fn to_ecam_addr(self) -> u64 {
        let v = self.0 as u64;
        ((v & 0xff_ff00) << 4) | (v & 0xfc)
    }
}

#[derive(Debug)]
pub struct PciIoBus {
    address: AtomicU32,
    segment: Arc<PciSegment>,
}

impl Mmio for PciIoBus {
    fn size(&self) -> u64 {
        8
    }

    fn read(&self, offset: u64, size: u8) -> Result<u64, mem::Error> {
        match offset {
            0 => {
                assert_eq!(size, 4);
                Ok(self.address.load(Ordering::Acquire) as u64)
            }
            4..=7 => {
                let addr = Address(self.address.load(Ordering::Acquire));
                self.segment
                    .read(addr.to_ecam_addr() | (offset & 0b11), size)
            }
            _ => Ok(0),
        }
    }

    fn write(&self, offset: u64, size: u8, val: u64) -> mem::Result<Action> {
        match offset {
            0 => {
                assert_eq!(size, 4);
                self.address.store(val as u32, Ordering::Release);
                Ok(Action::None)
            }
            4..=7 => {
                let addr = Address(self.address.load(Ordering::Acquire));
                self.segment
                    .write(addr.to_ecam_addr() | (offset & 0b11), size, val)
            }
            _ => Ok(Action::None),
        }
    }
}

#[derive(Debug)]
pub struct PciBus {
    pub io_bus: Arc<PciIoBus>,
    pub segment: Arc<PciSegment>,
}

impl PciBus {
    pub fn new() -> Self {
        let segment = Arc::new(PciSegment::new());

        #[cfg(target_arch = "x86_64")]
        segment.add(
            Bdf(0),
            PciDevice::new("host_bridge", Arc::new(HostBridge::new())),
        );

        PciBus {
            io_bus: Arc::new(PciIoBus {
                address: AtomicU32::new(0),
                segment: segment.clone(),
            }),
            segment,
        }
    }

    pub fn reserve(&self, bdf: Option<Bdf>) -> Option<Bdf> {
        self.segment.reserve(bdf)
    }

    pub fn add(&self, bdf: Bdf, dev: PciDevice) -> Option<PciDevice> {
        self.segment.add(bdf, dev)
    }
}

impl Default for PciBus {
    fn default() -> Self {
        Self::new()
    }
}

1	// Copyright 2024 Google LLC
2	//
3	// Licensed under the Apache License, Version 2.0 (the "License");
4	// you may not use this file except in compliance with the License.
5	// You may obtain a copy of the License at
6	//
7	// https://www.apache.org/licenses/LICENSE-2.0
8	//
9	// Unless required by applicable law or agreed to in writing, software
10	// distributed under the License is distributed on an "AS IS" BASIS,
11	// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12	// See the License for the specific language governing permissions and
13	// limitations under the License.
14
15	use std::sync::Arc;
16	use std::sync::atomic::{AtomicU32, Ordering};
17
18	use bitfield::bitfield;
19
20	use crate::mem;
21	use crate::mem::emulated::{Action, Mmio};
22	#[cfg(target_arch = "x86_64")]
23	use crate::pci::host_bridge::HostBridge;
24	use crate::pci::segment::PciSegment;
25	use crate::pci::{Bdf, PciDevice, Result};
26
27	bitfield! {
28	#[derive(Copy, Clone, Default)]
29	struct Address(u32);
30	impl Debug;
31	enabled, _: 31;
32	bus, _: 23, 16;
33	dev, _: 15, 11;
34	func, _: 10, 8;
35	offset, _: 7, 0;
36	}
37
38	impl Address {
39	pub fn to_ecam_addr(self) -> u64 {	×
40	let v = self.0 as u64;	×
41	((v & 0xff_ff00) << 4) \| (v & 0xfc)	×
42	}
43	}
44
45	#[derive(Debug)]
46	pub struct PciIoBus {
47	address: AtomicU32,
48	segment: Arc<PciSegment>,
49	}
50
51	impl Mmio for PciIoBus {
52	fn size(&self) -> u64 {	×
53	8
54	}
55
56	fn read(&self, offset: u64, size: u8) -> Result<u64, mem::Error> {	×
57	match offset {	×
58	0 => {
59	assert_eq!(size, 4);	×
60	Ok(self.address.load(Ordering::Acquire) as u64)	×
61	}
62	4..=7 => {	×
63	let addr = Address(self.address.load(Ordering::Acquire));	×
64	self.segment	×
65	.read(addr.to_ecam_addr() \| (offset & 0b11), size)	×
66	}
67	_ => Ok(0),	×
68	}
69	}
70
71	fn write(&self, offset: u64, size: u8, val: u64) -> mem::Result<Action> {	×
72	match offset {	×
73	0 => {
74	assert_eq!(size, 4);	×
75	self.address.store(val as u32, Ordering::Release);	×
76	Ok(Action::None)	×
77	}
78	4..=7 => {	×
79	let addr = Address(self.address.load(Ordering::Acquire));	×
80	self.segment	×
81	.write(addr.to_ecam_addr() \| (offset & 0b11), size, val)	×
82	}
83	_ => Ok(Action::None),	×
84	}
85	}
86	}
87
88	#[derive(Debug)]
89	pub struct PciBus {
90	pub io_bus: Arc<PciIoBus>,
91	pub segment: Arc<PciSegment>,
92	}
93
94	impl PciBus {
95	pub fn new() -> Self {	×
NEW 96	let segment = Arc::new(PciSegment::new());	×
97
98	#[cfg(target_arch = "x86_64")]
99	segment.add(
100	Bdf(0),
101	PciDevice::new("host_bridge", Arc::new(HostBridge::new())),
102	);
103
104	PciBus {
105	io_bus: Arc::new(PciIoBus {	×
106	address: AtomicU32::new(0),
107	segment: segment.clone(),
108	}),
109	segment,
110	}
111	}
112
NEW 113	pub fn reserve(&self, bdf: Option<Bdf>) -> Option<Bdf> {	×
NEW 114	self.segment.reserve(bdf)	×
115	}
116
117	pub fn add(&self, bdf: Bdf, dev: PciDevice) -> Option<PciDevice> {	×
118	self.segment.add(bdf, dev)	×
119	}
120	}
121
122	impl Default for PciBus {
123	fn default() -> Self {	×
124	Self::new()	×
125	}
126	}

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