17385983897

Committed 01 Sep 2025 07:41PM UTC coverage: 18.009% (-0.1%) from 18.149%

Build # 17385983897

Build Type

Pull #281

github

Committed by

web-flow

Commit Message

Merge 782c57b11 into 6ec9a6d6b

Pull Request Pull Request #281: Port to Apple Hypervisor framework

Run Details

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/alioth/src/hv/hvf/vcpu/vmexit.rs

// Copyright 2024 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

use snafu::ResultExt;

use crate::arch::psci::{PSCI_VERSION_1_1, PsciFunc, PsciMigrateInfo};
use crate::arch::reg::{EsrEl2DataAbort, EsrEl2Ec, MpidrEl1, Reg};
use crate::hv::hvf::bindings::{HvReg, HvVcpuExitException, hv_vcpu_get_reg};
use crate::hv::hvf::check_ret;
use crate::hv::hvf::vcpu::HvfVcpu;
use crate::hv::hvf::vm::VcpuEvent;
use crate::hv::{Result, Vcpu, VmExit, error};

impl HvfVcpu {
    // https://esr.arm64.dev/
    pub fn handle_exception(&mut self, exception: &HvVcpuExitException) -> Result<()> {
        let esr = exception.syndrome;
        match esr.ec() {
            EsrEl2Ec::DATA_ABORT_LOWER => {
                self.decode_data_abort(EsrEl2DataAbort(esr.iss()), exception.physical_address)
            }
            EsrEl2Ec::HVC_64 => self.handle_hvc(),
            _ => error::VmExit {
                msg: format!("Unhandled ESR: {esr:x?}"),
            }
            .fail(),
        }
    }

    pub fn decode_data_abort(&mut self, iss: EsrEl2DataAbort, gpa: u64) -> Result<()> {
        if !iss.isv() {
            return error::VmExit {
                msg: format!("Unhandled iss: {iss:x?}"),
            }
            .fail();
        }
        let reg = HvReg::from(iss.srt());
        let write = if iss.wnr() {
            let mut value = 0;
            let ret = unsafe { hv_vcpu_get_reg(self.vcpu_id, reg, &mut value) };
            check_ret(ret).context(error::VcpuReg)?;
            Some(value)
        } else {
            self.exit_reg = Some(reg);
            None
        };
        self.vmexit = Some(VmExit::Mmio {
            addr: gpa as _,
            write,
            size: 1 << iss.sas(),
        });
        let pc = self.get_reg(Reg::Pc)?;
        self.set_regs(&[(Reg::Pc, pc + 4)])
    }

    pub fn handle_hvc(&mut self) -> Result<()> {
        let func = self.get_reg(Reg::X0)?;
        let ret = match PsciFunc::from(func as u32) {
            PsciFunc::PSCI_VERSION => PSCI_VERSION_1_1 as u64,
            PsciFunc::MIGRATE_INFO_TYPE => PsciMigrateInfo::NOT_REQUIRED.raw() as u64,
            PsciFunc::PSCI_FEATURES => {
                let f = self.get_reg(Reg::X1)?;
                match PsciFunc::from(f as u32) {
                    PsciFunc::PSCI_VERSION
                    | PsciFunc::MIGRATE_INFO_TYPE
                    | PsciFunc::PSCI_FEATURES
                    | PsciFunc::SYSTEM_OFF
                    | PsciFunc::SYSTEM_OFF2_32
                    | PsciFunc::SYSTEM_OFF2_64
                    | PsciFunc::CPU_ON_32
                    | PsciFunc::CPU_ON_64 => 0,
                    _ => u64::MAX,
                }
            }
            PsciFunc::SYSTEM_OFF | PsciFunc::SYSTEM_OFF2_32 | PsciFunc::SYSTEM_OFF2_64 => {
                self.vmexit = Some(VmExit::Shutdown);
                return Ok(());
            }
            PsciFunc::CPU_ON_32 | PsciFunc::CPU_ON_64 => {
                let mpidr = self.get_reg(Reg::X1)?;
                let pc = self.get_reg(Reg::X2)?;
                let context = self.get_reg(Reg::X3)?;
                if let Some(sender) = self.senders.lock().get(&MpidrEl1(mpidr)) {
                    sender.send(VcpuEvent::PowerOn { pc, context }).unwrap();
                    0
                } else {
                    log::error!("Failed to find CPU with mpidr {mpidr:#x}");
                    u64::MAX
                }
            }
            f => {
                return error::VmExit {
                    msg: format!("HVC: {f:x?}"),
                }
                .fail();
            }
        };
        self.set_regs(&[(Reg::X0, ret)])
    }
}

1	// Copyright 2024 Google LLC
2	//
3	// Licensed under the Apache License, Version 2.0 (the "License");
4	// you may not use this file except in compliance with the License.
5	// You may obtain a copy of the License at
6	//
7	// https://www.apache.org/licenses/LICENSE-2.0
8	//
9	// Unless required by applicable law or agreed to in writing, software
10	// distributed under the License is distributed on an "AS IS" BASIS,
11	// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12	// See the License for the specific language governing permissions and
13	// limitations under the License.
14
15	use snafu::ResultExt;
16
17	use crate::arch::psci::{PSCI_VERSION_1_1, PsciFunc, PsciMigrateInfo};
18	use crate::arch::reg::{EsrEl2DataAbort, EsrEl2Ec, MpidrEl1, Reg};
19	use crate::hv::hvf::bindings::{HvReg, HvVcpuExitException, hv_vcpu_get_reg};
20	use crate::hv::hvf::check_ret;
21	use crate::hv::hvf::vcpu::HvfVcpu;
22	use crate::hv::hvf::vm::VcpuEvent;
23	use crate::hv::{Result, Vcpu, VmExit, error};
24
25	impl HvfVcpu {
26	// https://esr.arm64.dev/
NEW 27	pub fn handle_exception(&mut self, exception: &HvVcpuExitException) -> Result<()> {	×
28	let esr = exception.syndrome;	×
29	match esr.ec() {	×
30	EsrEl2Ec::DATA_ABORT_LOWER => {
31	self.decode_data_abort(EsrEl2DataAbort(esr.iss()), exception.physical_address)	×
32	}
NEW 33	EsrEl2Ec::HVC_64 => self.handle_hvc(),	×
34	_ => error::VmExit {
NEW 35	msg: format!("Unhandled ESR: {esr:x?}"),	×
36	}
37	.fail(),
38	}
39	}
40
NEW 41	pub fn decode_data_abort(&mut self, iss: EsrEl2DataAbort, gpa: u64) -> Result<()> {	×
42	if !iss.isv() {	×
NEW 43	return error::VmExit {	×
NEW 44	msg: format!("Unhandled iss: {iss:x?}"),	×
45	}
46	.fail();
47	}
48	let reg = HvReg::from(iss.srt());	×
49	let write = if iss.wnr() {	×
50	let mut value = 0;	×
51	let ret = unsafe { hv_vcpu_get_reg(self.vcpu_id, reg, &mut value) };	×
NEW 52	check_ret(ret).context(error::VcpuReg)?;	×
53	Some(value)	×
54	} else {
NEW 55	self.exit_reg = Some(reg);	×
56	None
57	};
58	self.vmexit = Some(VmExit::Mmio {
59	addr: gpa as _,
60	write,
61	size: 1 << iss.sas(),
62	});
NEW 63	let pc = self.get_reg(Reg::Pc)?;	×
64	self.set_regs(&[(Reg::Pc, pc + 4)])
65	}
66
NEW 67	pub fn handle_hvc(&mut self) -> Result<()> {	×
NEW 68	let func = self.get_reg(Reg::X0)?;	×
NEW 69	let ret = match PsciFunc::from(func as u32) {	×
NEW 70	PsciFunc::PSCI_VERSION => PSCI_VERSION_1_1 as u64,	×
NEW 71	PsciFunc::MIGRATE_INFO_TYPE => PsciMigrateInfo::NOT_REQUIRED.raw() as u64,	×
72	PsciFunc::PSCI_FEATURES => {
NEW 73	let f = self.get_reg(Reg::X1)?;	×
74	match PsciFunc::from(f as u32) {
75	PsciFunc::PSCI_VERSION
76	\| PsciFunc::MIGRATE_INFO_TYPE
77	\| PsciFunc::PSCI_FEATURES
78	\| PsciFunc::SYSTEM_OFF
79	\| PsciFunc::SYSTEM_OFF2_32
80	\| PsciFunc::SYSTEM_OFF2_64
81	\| PsciFunc::CPU_ON_32
NEW 82	\| PsciFunc::CPU_ON_64 => 0,	×
NEW 83	_ => u64::MAX,	×
84	}
85	}
86	PsciFunc::SYSTEM_OFF \| PsciFunc::SYSTEM_OFF2_32 \| PsciFunc::SYSTEM_OFF2_64 => {
NEW 87	self.vmexit = Some(VmExit::Shutdown);	×
NEW 88	return Ok(());	×
89	}
90	PsciFunc::CPU_ON_32 \| PsciFunc::CPU_ON_64 => {
NEW 91	let mpidr = self.get_reg(Reg::X1)?;	×
NEW 92	let pc = self.get_reg(Reg::X2)?;	×
NEW 93	let context = self.get_reg(Reg::X3)?;	×
NEW 94	if let Some(sender) = self.senders.lock().get(&MpidrEl1(mpidr)) {	×
95	sender.send(VcpuEvent::PowerOn { pc, context }).unwrap();
96	0
97	} else {
NEW 98	log::error!("Failed to find CPU with mpidr {mpidr:#x}");	×
NEW 99	u64::MAX	×
100	}
101	}
NEW 102	f => {	×
NEW 103	return error::VmExit {	×
NEW 104	msg: format!("HVC: {f:x?}"),	×
105	}
NEW 106	.fail();	×
107	}
108	};
109	self.set_regs(&[(Reg::X0, ret)])
110	}
111	}

google / alioth / 17385983897

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