17185180867

Committed 24 Aug 2025 06:16AM UTC coverage: 13.911% (+0.02%) from 13.887%

Build # 17185180867

Build Type

Pull #277

github

Committed by

web-flow

Commit Message

Merge 15d9ad867 into 861f19073

Pull Request Pull Request #277: feat: Unix domain socket based vsock device

Run Details

50 of 86 new or added lines in 9 files covered. (58.14%)

69 existing lines in 6 files now uncovered.

977 of 7023 relevant lines covered (13.91%)

17.72 hits per line

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100.0

/alioth/src/virtio/queue/split_test.rs

// Copyright 2025 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

use std::ptr::eq as ptr_eq;
use std::sync::atomic::Ordering;

use assert_matches::assert_matches;
use rstest::rstest;

use crate::mem::mapped::RamBus;
use crate::virtio::queue::private::VirtQueuePrivate;
use crate::virtio::queue::split::{Desc, DescFlag, SplitQueue};
use crate::virtio::queue::tests::VirtQueueGuest;
use crate::virtio::queue::{QueueReg, VirtQueue};
use crate::virtio::tests::{DATA_ADDR, fixture_queue, fixture_ram_bus};

impl<'r, 'm> VirtQueueGuest<'m> for SplitQueue<'r, 'm> {
    fn add_desc(&mut self, index: u16, id: u16, readable: &[(u64, u32)], writable: &[(u64, u32)]) {
        let readable_count = readable.len();
        let total_count = readable.len() + writable.len();
        for (i, (addr, len)) in readable.iter().chain(writable.iter()).enumerate() {
            let mut flag = DescFlag::empty();
            if i < total_count - 1 {
                flag |= DescFlag::NEXT;
            }
            if i >= readable_count {
                flag |= DescFlag::WRITE;
            }
            let desc = Desc {
                addr: *addr,
                len: *len,
                flag: flag.bits(),
                next: id + i as u16 + 1,
            };
            *unsafe { &mut *self.desc.offset((id + i as u16) as isize) } = desc;
        }
        let avail_idx = self.avail_index();
        assert_eq!(index, avail_idx);
        *unsafe { &mut *self.avail_ring.offset((avail_idx % self.size) as isize) } = id;
        unsafe { &mut *self.avail_hdr }.idx = avail_idx.wrapping_add(1);
    }
}

#[rstest]
fn disabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
    let ram = fixture_ram_bus.lock_layout();
    fixture_queue.enabled.store(false, Ordering::Relaxed);
    let split_queue = SplitQueue::new(&fixture_queue, &*ram, false);
    assert_matches!(split_queue, Ok(None));
}

#[rstest]
fn enabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
    let ram = fixture_ram_bus.lock_layout();
    let mut q = SplitQueue::new(&fixture_queue, &*ram, false)
        .unwrap()
        .unwrap();
    assert!(ptr_eq(q.reg(), &fixture_queue));

    let str_0 = "Hello, World!";
    let str_1 = "Goodbye, World!";
    let str_2 = "Bose-Einstein condensate";
    let addr_0 = DATA_ADDR;
    let addr_1 = addr_0 + str_0.len() as u64;
    let addr_2 = addr_1 + str_1.len() as u64;
    ram.write(addr_0, str_0.as_bytes()).unwrap();
    ram.write(addr_1, str_1.as_bytes()).unwrap();

    q.add_desc(
        0,
        0,
        &[(addr_0, str_0.len() as u32), (addr_1, str_1.len() as u32)],
        &[],
    );

    assert_eq!(q.avail_index(), 1);
    assert!(q.desc_avail(0));
    let chain = q.get_desc_chain(0).unwrap().unwrap();
    assert_eq!(chain.id, 0);
    assert_eq!(&*chain.readable[0], str_0.as_bytes());
    assert_eq!(&*chain.readable[1], str_1.as_bytes());
    assert_eq!(chain.writable.len(), 0);
    q.push_used(chain, 0);
    assert!(!q.desc_avail(1));

    q.add_desc(1, 2, &[], &[(addr_2, str_2.len() as u32)]);
    let mut chain = q.get_desc_chain(1).unwrap().unwrap();
    assert_eq!(chain.id, 2);
    assert_eq!(chain.readable.len(), 0);
    let buffer = chain.writable[0].as_mut();
    buffer.copy_from_slice(str_2.as_bytes());
    q.push_used(chain, str_2.len() as u32);
    let mut b = vec![0u8; str_2.len()];
    ram.read(addr_2, b.as_mut()).unwrap();
    assert_eq!(&b, str_2.as_bytes());
}

#[rstest]
fn event_idx_enabled(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
    let ram = fixture_ram_bus.lock_layout();
    let q = SplitQueue::new(&fixture_queue, &*ram, true)
        .unwrap()
        .unwrap();
    unsafe { *q.used_event.unwrap() = 1 };
    assert_eq!(q.used_event(), Some(1));

    assert!(q.set_avail_event(|event| *event = 12));
    assert_eq!(unsafe { *q.avail_event.unwrap() }, 12);
}

1	// Copyright 2025 Google LLC
2	//
3	// Licensed under the Apache License, Version 2.0 (the "License");
4	// you may not use this file except in compliance with the License.
5	// You may obtain a copy of the License at
6	//
7	// https://www.apache.org/licenses/LICENSE-2.0
8	//
9	// Unless required by applicable law or agreed to in writing, software
10	// distributed under the License is distributed on an "AS IS" BASIS,
11	// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12	// See the License for the specific language governing permissions and
13	// limitations under the License.
14
15	use std::ptr::eq as ptr_eq;
16	use std::sync::atomic::Ordering;
17
18	use assert_matches::assert_matches;
19	use rstest::rstest;
20
21	use crate::mem::mapped::RamBus;
22	use crate::virtio::queue::private::VirtQueuePrivate;
23	use crate::virtio::queue::split::{Desc, DescFlag, SplitQueue};
24	use crate::virtio::queue::tests::VirtQueueGuest;
25	use crate::virtio::queue::{QueueReg, VirtQueue};
26	use crate::virtio::tests::{DATA_ADDR, fixture_queue, fixture_ram_bus};
27
28	impl<'r, 'm> VirtQueueGuest<'m> for SplitQueue<'r, 'm> {
29	fn add_desc(&mut self, index: u16, id: u16, readable: &[(u64, u32)], writable: &[(u64, u32)]) {	29✔
30	let readable_count = readable.len();	85✔
31	let total_count = readable.len() + writable.len();	113✔
32	for (i, (addr, len)) in readable.iter().chain(writable.iter()).enumerate() {	207✔
UNCOV 33	let mut flag = DescFlag::empty();	1✔
34	if i < total_count - 1 {	10✔
35	flag \|= DescFlag::NEXT;	9✔
36	}
37	if i >= readable_count {	17✔
38	flag \|= DescFlag::WRITE;	17✔
39	}
40	let desc = Desc {
41	addr: *addr,	1✔
42	len: *len,	1✔
UNCOV 43	flag: flag.bits(),	1✔
44	next: id + i as u16 + 1,	2✔
45	};
UNCOV 46	unsafe { &mut self.desc.offset((id + i as u16) as isize) } = desc;	3✔
47	}
48	let avail_idx = self.avail_index();	85✔
49	assert_eq!(index, avail_idx);	29✔
50	unsafe { &mut self.avail_ring.offset((avail_idx % self.size) as isize) } = id;	86✔
51	unsafe { &mut *self.avail_hdr }.idx = avail_idx.wrapping_add(1);	58✔
52	}
53	}
54
55	#[rstest]
56	fn disabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
57	let ram = fixture_ram_bus.lock_layout();
58	fixture_queue.enabled.store(false, Ordering::Relaxed);
59	let split_queue = SplitQueue::new(&fixture_queue, &*ram, false);
60	assert_matches!(split_queue, Ok(None));
61	}
62
63	#[rstest]
64	fn enabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
65	let ram = fixture_ram_bus.lock_layout();
66	let mut q = SplitQueue::new(&fixture_queue, &*ram, false)
67	.unwrap()
68	.unwrap();
69	assert!(ptr_eq(q.reg(), &fixture_queue));
70
71	let str_0 = "Hello, World!";
72	let str_1 = "Goodbye, World!";
73	let str_2 = "Bose-Einstein condensate";
74	let addr_0 = DATA_ADDR;
75	let addr_1 = addr_0 + str_0.len() as u64;
76	let addr_2 = addr_1 + str_1.len() as u64;
77	ram.write(addr_0, str_0.as_bytes()).unwrap();
78	ram.write(addr_1, str_1.as_bytes()).unwrap();
79
80	q.add_desc(
81	0,
82	0,
83	&[(addr_0, str_0.len() as u32), (addr_1, str_1.len() as u32)],
84	&[],
85	);
86
87	assert_eq!(q.avail_index(), 1);
88	assert!(q.desc_avail(0));
89	let chain = q.get_desc_chain(0).unwrap().unwrap();
90	assert_eq!(chain.id, 0);
91	assert_eq!(&*chain.readable[0], str_0.as_bytes());
92	assert_eq!(&*chain.readable[1], str_1.as_bytes());
93	assert_eq!(chain.writable.len(), 0);
94	q.push_used(chain, 0);
95	assert!(!q.desc_avail(1));
96
97	q.add_desc(1, 2, &[], &[(addr_2, str_2.len() as u32)]);
98	let mut chain = q.get_desc_chain(1).unwrap().unwrap();
99	assert_eq!(chain.id, 2);
100	assert_eq!(chain.readable.len(), 0);
101	let buffer = chain.writable[0].as_mut();
102	buffer.copy_from_slice(str_2.as_bytes());
103	q.push_used(chain, str_2.len() as u32);
104	let mut b = vec![0u8; str_2.len()];
105	ram.read(addr_2, b.as_mut()).unwrap();
106	assert_eq!(&b, str_2.as_bytes());
107	}
108
109	#[rstest]
110	fn event_idx_enabled(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
111	let ram = fixture_ram_bus.lock_layout();
112	let q = SplitQueue::new(&fixture_queue, &*ram, true)
113	.unwrap()
114	.unwrap();
115	unsafe { *q.used_event.unwrap() = 1 };
116	assert_eq!(q.used_event(), Some(1));
117
118	assert!(q.set_avail_event(\|event\| *event = 12));
119	assert_eq!(unsafe { *q.avail_event.unwrap() }, 12);
120	}

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