17016642693

Committed 17 Aug 2025 04:19AM UTC coverage: 10.406% (-0.01%) from 10.419%

Build # 17016642693

Build Type

Pull #273

github

Committed by

web-flow

Commit Message

Merge ef274b67c into 3c18ccbb6

Pull Request Pull Request #273: feat: virtio packed queue

Run Details

50 of 111 new or added lines in 8 files covered. (45.05%)

97 existing lines in 5 files now uncovered.

713 of 6852 relevant lines covered (10.41%)

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100.0

/alioth/src/virtio/queue/split_test.rs

// Copyright 2025 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

use std::ptr::eq as ptr_eq;
use std::sync::atomic::Ordering;

use assert_matches::assert_matches;
use rstest::rstest;

use crate::mem::mapped::RamBus;
use crate::virtio::VirtioFeature;
use crate::virtio::queue::split::{Desc, DescFlag, SplitQueue};
use crate::virtio::queue::{QueueReg, VirtQueue};

use crate::virtio::queue::tests::{DATA_ADDR, QUEUE_SIZE, fixture_queue, fixture_ram_bus};

impl<'r, 'm> SplitQueue<'r, 'm> {
    pub fn add_desc(&mut self, id: u16, readable: &[(u64, u32)], writable: &[(u64, u32)]) {
        let readable_count = readable.len();
        let total_count = readable.len() + writable.len();
        for (i, (addr, len)) in readable.iter().chain(writable.iter()).enumerate() {
            let mut flag = DescFlag::empty();
            if i < total_count - 1 {
                flag |= DescFlag::NEXT;
            }
            if i >= readable_count {
                flag |= DescFlag::WRITE;
            }
            let desc = Desc {
                addr: *addr,
                len: *len,
                flag: flag.bits(),
                next: id + i as u16 + 1,
            };
            *unsafe { &mut *self.desc.offset((id + i as u16) as isize) } = desc;
        }
        let avail_idx = self.avail_index();
        *unsafe { &mut *self.avail_ring.offset((avail_idx % self.size) as isize) } = id;
        unsafe { &mut *self.avail_hdr }.idx = avail_idx.wrapping_add(1);
    }
}

#[rstest]
fn disabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
    let ram = fixture_ram_bus.lock_layout();
    fixture_queue.enabled.store(false, Ordering::Relaxed);
    let split_queue = SplitQueue::new(&fixture_queue, &*ram, 0);
    assert_matches!(split_queue, Ok(None));
}

#[rstest]
fn enabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
    let ram = fixture_ram_bus.lock_layout();
    let mut q = SplitQueue::new(&fixture_queue, &*ram, 0).unwrap().unwrap();
    assert!(ptr_eq(q.reg(), &fixture_queue));
    assert_eq!(q.size(), QUEUE_SIZE);

    let str_0 = "Hello, World!";
    let str_1 = "Goodbye, World!";
    let str_2 = "Bose-Einstein condensate";
    let addr_0 = DATA_ADDR;
    let addr_1 = addr_0 + str_0.len() as u64;
    let addr_2 = addr_1 + str_1.len() as u64;
    ram.write(addr_0, str_0.as_bytes()).unwrap();
    ram.write(addr_1, str_1.as_bytes()).unwrap();

    q.add_desc(
        0,
        &[(addr_0, str_0.len() as u32), (addr_1, str_1.len() as u32)],
        &[],
    );

    assert_eq!(q.avail_index(), 1);
    assert_eq!(q.read_avail(0), 0);
    assert!(q.has_next_desc());
    let chain = q.next_desc_chain().unwrap().unwrap();
    assert_eq!(chain.id, 0);
    assert_eq!(&*chain.readable[0], str_0.as_bytes());
    assert_eq!(&*chain.readable[1], str_1.as_bytes());
    assert_eq!(chain.writable.len(), 0);
    q.push_used(chain, 0);
    assert!(!q.has_next_desc());

    q.add_desc(2, &[], &[(addr_2, str_2.len() as u32)]);
    let mut chain = q.next_desc_chain().unwrap().unwrap();
    assert_eq!(chain.id, 2);
    assert_eq!(chain.readable.len(), 0);
    let buffer = chain.writable[0].as_mut();
    buffer.copy_from_slice(str_2.as_bytes());
    q.push_used(chain, str_2.len() as u32);
    let mut b = vec![0u8; str_2.len()];
    ram.read(addr_2, b.as_mut()).unwrap();
    assert_eq!(&b, str_2.as_bytes());
}

#[rstest]
fn event_idx_enabled(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
    let ram = fixture_ram_bus.lock_layout();
    let q = SplitQueue::new(&fixture_queue, &*ram, VirtioFeature::EVENT_IDX.bits())
        .unwrap()
        .unwrap();
    unsafe { *q.used_event.unwrap() = 1 };
    assert_eq!(q.used_event(), Some(1));

    assert_eq!(q.set_avail_event(12), Some(()));
    assert_eq!(unsafe { *q.avail_event.unwrap() }, 12);
}

1	// Copyright 2025 Google LLC
2	//
3	// Licensed under the Apache License, Version 2.0 (the "License");
4	// you may not use this file except in compliance with the License.
5	// You may obtain a copy of the License at
6	//
7	// https://www.apache.org/licenses/LICENSE-2.0
8	//
9	// Unless required by applicable law or agreed to in writing, software
10	// distributed under the License is distributed on an "AS IS" BASIS,
11	// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12	// See the License for the specific language governing permissions and
13	// limitations under the License.
14
15	use std::ptr::eq as ptr_eq;
16	use std::sync::atomic::Ordering;
17
18	use assert_matches::assert_matches;
19	use rstest::rstest;
20
21	use crate::mem::mapped::RamBus;
22	use crate::virtio::VirtioFeature;
23	use crate::virtio::queue::split::{Desc, DescFlag, SplitQueue};
24	use crate::virtio::queue::{QueueReg, VirtQueue};
25
26	use crate::virtio::queue::tests::{DATA_ADDR, QUEUE_SIZE, fixture_queue, fixture_ram_bus};
27
28	impl<'r, 'm> SplitQueue<'r, 'm> {
29	pub fn add_desc(&mut self, id: u16, readable: &[(u64, u32)], writable: &[(u64, u32)]) {	21✔
30	let readable_count = readable.len();	61✔
31	let total_count = readable.len() + writable.len();	81✔
32	for (i, (addr, len)) in readable.iter().chain(writable.iter()).enumerate() {	151✔
UNCOV 33	let mut flag = DescFlag::empty();	1✔
34	if i < total_count - 1 {	9✔
35	flag \|= DescFlag::NEXT;	7✔
36	}
37	if i >= readable_count {	13✔
38	flag \|= DescFlag::WRITE;	13✔
39	}
40	let desc = Desc {
41	addr: *addr,	2✔
42	len: *len,	3✔
43	flag: flag.bits(),	3✔
UNCOV 44	next: id + i as u16 + 1,	6✔
45	};
UNCOV 46	unsafe { &mut self.desc.offset((id + i as u16) as isize) } = desc;	9✔
47	}
48	let avail_idx = self.avail_index();	63✔
49	unsafe { &mut self.avail_ring.offset((avail_idx % self.size) as isize) } = id;	63✔
50	unsafe { &mut *self.avail_hdr }.idx = avail_idx.wrapping_add(1);	46✔
51	}
52	}
53
54	#[rstest]
55	fn disabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
56	let ram = fixture_ram_bus.lock_layout();
57	fixture_queue.enabled.store(false, Ordering::Relaxed);
58	let split_queue = SplitQueue::new(&fixture_queue, &*ram, 0);
59	assert_matches!(split_queue, Ok(None));
60	}
61
62	#[rstest]
63	fn enabled_queue(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
64	let ram = fixture_ram_bus.lock_layout();
65	let mut q = SplitQueue::new(&fixture_queue, &*ram, 0).unwrap().unwrap();
66	assert!(ptr_eq(q.reg(), &fixture_queue));
67	assert_eq!(q.size(), QUEUE_SIZE);
68
69	let str_0 = "Hello, World!";
70	let str_1 = "Goodbye, World!";
71	let str_2 = "Bose-Einstein condensate";
72	let addr_0 = DATA_ADDR;
73	let addr_1 = addr_0 + str_0.len() as u64;
74	let addr_2 = addr_1 + str_1.len() as u64;
75	ram.write(addr_0, str_0.as_bytes()).unwrap();
76	ram.write(addr_1, str_1.as_bytes()).unwrap();
77
78	q.add_desc(
79	0,
80	&[(addr_0, str_0.len() as u32), (addr_1, str_1.len() as u32)],
81	&[],
82	);
83
84	assert_eq!(q.avail_index(), 1);
85	assert_eq!(q.read_avail(0), 0);
86	assert!(q.has_next_desc());
87	let chain = q.next_desc_chain().unwrap().unwrap();
88	assert_eq!(chain.id, 0);
89	assert_eq!(&*chain.readable[0], str_0.as_bytes());
90	assert_eq!(&*chain.readable[1], str_1.as_bytes());
91	assert_eq!(chain.writable.len(), 0);
92	q.push_used(chain, 0);
93	assert!(!q.has_next_desc());
94
95	q.add_desc(2, &[], &[(addr_2, str_2.len() as u32)]);
96	let mut chain = q.next_desc_chain().unwrap().unwrap();
97	assert_eq!(chain.id, 2);
98	assert_eq!(chain.readable.len(), 0);
99	let buffer = chain.writable[0].as_mut();
100	buffer.copy_from_slice(str_2.as_bytes());
101	q.push_used(chain, str_2.len() as u32);
102	let mut b = vec![0u8; str_2.len()];
103	ram.read(addr_2, b.as_mut()).unwrap();
104	assert_eq!(&b, str_2.as_bytes());
105	}
106
107	#[rstest]
108	fn event_idx_enabled(fixture_ram_bus: RamBus, fixture_queue: QueueReg) {
109	let ram = fixture_ram_bus.lock_layout();
110	let q = SplitQueue::new(&fixture_queue, &*ram, VirtioFeature::EVENT_IDX.bits())
111	.unwrap()
112	.unwrap();
113	unsafe { *q.used_event.unwrap() = 1 };
114	assert_eq!(q.used_event(), Some(1));
115
116	assert_eq!(q.set_avail_event(12), Some(()));
117	assert_eq!(unsafe { *q.avail_event.unwrap() }, 12);
118	}

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