15758827329

Committed 19 Jun 2025 01:13PM UTC coverage: 93.936% (-5.1%) from 98.992%

Build # 15758827329

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Commit Message

Merge pull request #41 from nbiotcloud/38-add-wordiotype

38 add wordiotype

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383 of 392 new or added lines in 2 files covered. (97.7%)

39 existing lines in 4 files now uncovered.

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46.88

/src/ucdp_regf/examples/simple/uart/uart.py

#
# MIT License
#
# Copyright (c) 2024-2025 nbiotcloud
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
"""UART Example."""

from typing import ClassVar

import ucdp as u
from fileliststandard import HdlFileList
from glbl.bus import BusType
from glbl.clk_gate import ClkGateMod
from glbl.regf import RegfMod


class UartIoType(u.AStructType):
    """UART IO."""

    title: str = "UART"
    comment: str = "RX/TX"

    def _build(self) -> None:
        self._add("rx", u.BitType(), u.BWD)
        self._add("tx", u.BitType(), u.FWD)


class UartMod(u.AMod):
    """A Simple UART."""

    filelists: ClassVar[u.ModFileLists] = (HdlFileList(gen="full"),)

    def _build(self) -> None:
        self.add_port(u.ClkRstAnType(), "main_i")
        self.add_port(UartIoType(), "uart_o")
        self.add_port(BusType(), "bus_i")

        # Power-Save Clock Gate
        clkgate = ClkGateMod(self, "u_clk_gate")
        clkgate.con("clk_i", "main_clk_i")
        clkgate.con("clk_o", "create(clk_s)")

        # Register File
        regf = RegfMod(self, "u_regf")
        regf.con("main_i", "main_i")

        word = regf.add_word("ctrl")
        word.add_field("ena", u.EnaType(), "RW", route="u_clk_gate/ena_i")
        word.add_field("busy", u.BusyType(), "RO", align=4, route="create(u_core/busy_o)")

        # Core
        core = UartCoreMod(self, "u_core")
        core.add_port(u.ClkRstAnType(), "main_i")
        core.con("main_clk_i", "clk_s")
        core.con("main_rst_an_i", "main_rst_an_i")


class UartCoreMod(u.ACoreMod):
    """Core Layer."""

    filelists: ClassVar[u.ModFileLists] = (HdlFileList(gen="inplace"),)

1	#
2	# MIT License
3	#
4	# Copyright (c) 2024-2025 nbiotcloud
5	#
6	# Permission is hereby granted, free of charge, to any person obtaining a copy
7	# of this software and associated documentation files (the "Software"), to deal
8	# in the Software without restriction, including without limitation the rights
9	# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10	# copies of the Software, and to permit persons to whom the Software is
11	# furnished to do so, subject to the following conditions:
12	#
13	# The above copyright notice and this permission notice shall be included in all
14	# copies or substantial portions of the Software.
15	#
16	# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19	# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20	# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21	# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22	# SOFTWARE.
23	#
24	"""UART Example."""
25
26	from typing import ClassVar	12✔
27
28	import ucdp as u	12✔
29	from fileliststandard import HdlFileList	12✔
30	from glbl.bus import BusType	12✔
31	from glbl.clk_gate import ClkGateMod	12✔
32	from glbl.regf import RegfMod	12✔
33
34
35	class UartIoType(u.AStructType):	12✔
36	"""UART IO."""
37
38	title: str = "UART"	12✔
39	comment: str = "RX/TX"	12✔
40
41	def _build(self) -> None:	12✔
UNCOV 42	self._add("rx", u.BitType(), u.BWD)	×
UNCOV 43	self._add("tx", u.BitType(), u.FWD)	×
44
45
46	class UartMod(u.AMod):	12✔
47	"""A Simple UART."""
48
49	filelists: ClassVar[u.ModFileLists] = (HdlFileList(gen="full"),)	12✔
50
51	def _build(self) -> None:	12✔
UNCOV 52	self.add_port(u.ClkRstAnType(), "main_i")	×
UNCOV 53	self.add_port(UartIoType(), "uart_o")	×
UNCOV 54	self.add_port(BusType(), "bus_i")	×
55
56	# Power-Save Clock Gate
UNCOV 57	clkgate = ClkGateMod(self, "u_clk_gate")	×
UNCOV 58	clkgate.con("clk_i", "main_clk_i")	×
UNCOV 59	clkgate.con("clk_o", "create(clk_s)")	×
60
61	# Register File
UNCOV 62	regf = RegfMod(self, "u_regf")	×
UNCOV 63	regf.con("main_i", "main_i")	×
64
UNCOV 65	word = regf.add_word("ctrl")	×
UNCOV 66	word.add_field("ena", u.EnaType(), "RW", route="u_clk_gate/ena_i")	×
UNCOV 67	word.add_field("busy", u.BusyType(), "RO", align=4, route="create(u_core/busy_o)")	×
68
69	# Core
UNCOV 70	core = UartCoreMod(self, "u_core")	×
UNCOV 71	core.add_port(u.ClkRstAnType(), "main_i")	×
UNCOV 72	core.con("main_clk_i", "clk_s")	×
UNCOV 73	core.con("main_rst_an_i", "main_rst_an_i")	×
74
75
76	class UartCoreMod(u.ACoreMod):	12✔
77	"""Core Layer."""
78
79	filelists: ClassVar[u.ModFileLists] = (HdlFileList(gen="inplace"),)	12✔

nbiotcloud / ucdp-regf / 15758827329

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