8b945dd2-6cbf-43b3-be54-881b32d4f5e4

Committed 10 Jun 2025 09:35PM UTC coverage: 84.734% (-2.6%) from 87.284%

Build # 8b945dd2-6cbf-43b3-be54-881b32d4f5e4

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circleci

Committed by

Nic30

Commit Message

test: fix call of unittestMain

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74.16

/hwt/code.py

from operator import and_, or_, xor, add, eq
from types import GeneratorType
from typing import Union, Sequence, Optional, Tuple

from hdlConvertorAst.to.hdlUtils import iter_with_last
from hwt.code_utils import _mkOp, _HwIOToRtlSignal
from hwt.hdl.const import HConst
from hwt.hdl.operatorDefs import concatFn
from hwt.hdl.statements.codeBlockContainer import HdlStmCodeBlockContainer
from hwt.hdl.statements.ifContainter import IfContainer
from hwt.hdl.statements.statement import HwtSyntaxError, HdlStatement
from hwt.hdl.statements.switchContainer import SwitchContainer
from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement
from hwt.hdl.types.bits import HBits
from hwt.hdl.types.enum import HEnum
from hwt.hdl.types.typeCast import toHVal
from hwt.mainBases import HwIOBase, HwModuleBase
from hwt.mainBases import RtlSignalBase
from hwt.math import log2ceil
from hwt.pyUtils.arrayQuery import arr_any
from hwt.synthesizer.rtlLevel.rtlSignalWalkers import \
    discoverEventDependency


class CodeBlock(HdlStmCodeBlockContainer):
    """
    Container for list of statements
    """

    def __init__(self, *statements: Sequence[HdlStatement]):
        super(CodeBlock, self).__init__()
        self._register_stements(statements, self.statements)
        self.rank = sum(map(lambda s: s.rank, statements))

        if self._outputs:
            ctx = self._get_rtl_context()
            ctx.statements.add(self)


class If(IfContainer):
    """
    If statement generator
    """

    def __init__(self, cond: Union[RtlSignalBase, HwIOBase], *statements: Sequence[HdlStatement]):
        """
        :param cond: condition in if statement
        :param statements: list of statements which should be active
            if condition is met
        """
        cond_sig = _HwIOToRtlSignal(cond)
        if not isinstance(cond_sig, RtlSignalBase):
            raise HwtSyntaxError("Condition is not signal, it is not certain"
                                 " if this is an error or desire ", cond_sig)

        assert cond_sig._dtype.bit_length() == 1, cond_sig
        super(If, self).__init__(cond_sig)
        self.rank = 1
        self._inputs.append(cond_sig)
        cond_sig._rtlEndpoints.append(self)

        ev_dep = arr_any(discoverEventDependency(cond_sig), lambda x: True)
        self._event_dependent_from_branch = 0 if ev_dep else None

        self._register_stements(statements, self.ifTrue)
        self._get_rtl_context().statements.add(self)

    def Elif(self, cond: Union[RtlSignalBase, HwIOBase], *statements: Sequence[HdlStatement]):
        assert self.parentStm is None
        self.rank += 1
        cond_sig = _HwIOToRtlSignal(cond)

        assert cond_sig._dtype.bit_length() == 1, cond_sig
        ev_dep = arr_any(discoverEventDependency(cond_sig), lambda x: True)
        self._event_dependent_from_branch = len(self.elIfs) + 1 if ev_dep else None

        self._inputs.append(cond_sig)
        cond_sig._rtlEndpoints.append(self)

        stms = ListOfHdlStatement()
        self.elIfs.append((cond_sig, stms))
        self._register_stements(statements, stms)

        return self

    def Else(self, *statements: Sequence[HdlStatement]):
        assert self.parentStm is None
        if self.ifFalse is not None:
            raise HwtSyntaxError(
                "Else on this if-then-else statement was already used")

        self.rank += 1

        self.ifFalse = ListOfHdlStatement()
        self._register_stements(statements, self.ifFalse)
        return self


class Switch(SwitchContainer):
    """
    Switch statement generator
    """

    def __init__(self, switchOn: Union[RtlSignalBase, HwIOBase]):
        switchOn = _HwIOToRtlSignal(switchOn)
        if not isinstance(switchOn, RtlSignalBase):
            raise HwtSyntaxError("Select is not signal, it is not certain"
                                 " if this is an error or desire")
        if arr_any(discoverEventDependency(switchOn), lambda x: True):
            raise HwtSyntaxError("Can not switch on result of event operator")

        super(Switch, self).__init__(switchOn, [])
        switchOn._rtlCtx.statements.add(self)
        self._inputs.append(switchOn)
        switchOn._rtlEndpoints.append(self)

    def add_cases(self, tupesValStms: Sequence[Tuple[Union[HConst, int], Sequence[HdlStatement]]]):
        """
        Add multiple case statements from iterable of tuples
        (caseVal, statements)
        """
        s = self
        for val, statements in tupesValStms:
            s = s.Case(val, statements)
        return s

    def Case(self, caseVal: Union[HConst, int], *statements: Sequence[HdlStatement]):
        "c-like case of switch statement"
        assert self.parentStm is None
        caseVal = toHVal(caseVal, self.switchOn._dtype)

        assert isinstance(caseVal, HConst), caseVal
        assert caseVal._is_full_valid(), "Cmp with invalid value"
        assert caseVal not in self._case_value_index, (
            "Switch statement already has case for value ", caseVal)

        self.rank += 1
        stms = ListOfHdlStatement()
        self._case_value_index[caseVal] = len(self.cases)
        self.cases.append((caseVal, stms))
        self._register_stements(statements, stms)

        return self

    def Default(self, *statements: Sequence[HdlStatement]):
        """c-like default of switch statement
        """
        assert self.parentStm is None
        self.rank += 1
        self.default = ListOfHdlStatement()
        self._register_stements(statements, self.default)
        return self


def SwitchLogic(cases: Sequence[Tuple[Union[RtlSignalBase, HwIOBase, HConst, bool], Sequence[HdlStatement]]],
                default: Optional[Sequence[HdlStatement]]=None):
    """
    Generate if tree for cases like (syntax sugar for large generated elifs)

    ..code-block:: python
        if cond0:
            statements0
        elif cond1:
            statements1
        else:
            default

    :param case: iterable of tuples (condition, statements)
    :param default: default statements
    """
    assigTop = None
    hasElse = False
    for last, (cond, statements) in iter_with_last(cases):
        if isinstance(cond, (RtlSignalBase, HwIOBase)):
            if assigTop is None:
                assigTop = If(cond,
                             statements
                           )
            else:
                assigTop = assigTop.Elif(cond, statements)
        else:
            if cond:
                if assigTop is None:
                    assigTop = statements
                else:
                    assigTop.Else(statements)
                    hasElse = True

                if last or isinstance(cases, GeneratorType):
                    # allow True as a condition for default
                    break

            raise HwtSyntaxError("Condition is not a signal, it is not certain"
                                 " if this is an error or desire ", cond, cases)

    if assigTop is None:
        if default is None:
            return []
        else:
            return default
    else:
        if hasElse:
            return assigTop
        elif default is not None:
            assigTop = assigTop.Else(default)

        return assigTop


def In(sigOrConst: Union[RtlSignalBase, HwIOBase, HConst], iterable: Sequence[Union[RtlSignalBase, HwIOBase, HConst]]):
    """
    HDL convertible "in" operator, check if any of items
    in "iterable" equals "sigOrConst"
    """
    res = None
    for i in iterable:
        i = toHVal(i)
        if res is None:
            res = sigOrConst._eq(i)
        else:
            res = res | sigOrConst._eq(i)

    assert res is not None, "argument iterable is empty"
    return res


def StaticForEach(parentModule: HwModuleBase, items, bodyFn, name=""):
    """
    Generate for loop for static items

    :param parentModule: HwModule where this code should be instantiated
    :param items: items which this "for" iterating on
    :param bodyFn: function which fn(item, index) or fn(item)
        returns (statementList, ack).
        It's content is performed in every iteration.
        When ack is high loop will fall to next iteration
    """

    items = list(items)
    itemsCnt = len(items)
    if itemsCnt == 0:
        # if there are no items there is nothing to generate
        return []
    elif itemsCnt == 1:
        # if there is only one item do not generate counter logic generate
        return bodyFn(items[0], 0)
    else:
        # if there is multiple items we have to generate counter logic
        index = parentModule._reg(name + "for_index",
                                HBits(log2ceil(itemsCnt + 1), signed=False),
                                def_val=0)
        ackSig = parentModule._sig(name + "for_ack")

        statementLists = []
        for i, (statementList, ack) in [(i, bodyFn(item, i))
                                        for i, item in enumerate(items)]:
            statementLists.append(statementList + [(ackSig(ack)), ])

        If(ackSig,
           If(index._eq(itemsCnt - 1),
              index(0)
              ).Else(
               index(index + 1)
           )
           )

        return Switch(index)\
            .add_cases(
            enumerate(statementLists)
        ).Default(
            bodyFn(items[0], 0)[0],
            ackSig(True)
        )


class FsmBuilder(Switch):
    """
    A syntax sugar which automatically construct the state transition switch and state register

    :ivar ~.stateReg: register with state
    """

    def __init__(self, parentModule: HwModuleBase, stateT, stateRegName="st"):
        """
        :param parentModule: parent HwModule where FSM should be builded
        :param stateT: enum type of state
        :param stateRegName: name of register where sate is stored
        """
        if isinstance(stateT, HEnum):
            beginVal = stateT.from_py(stateT._allValues[0])
        else:
            beginVal = 0

        self.stateReg = parentModule._reg(stateRegName, stateT, beginVal)
        Switch.__init__(self, self.stateReg)

    def Trans(self, stateFrom, *condAndNextState):
        """
        :param stateFrom: apply when FSM is in this state
        :param condAndNextState: tuples (condition, newState),
            last does not to have condition

        :attention: transitions has priority, first has the biggest
        :attention: if stateFrom is None it is evaluated as default
        """
        top = []
        last = True

        for cAndS in reversed(condAndNextState):
            if last is True:
                last = False
                # if this is last trans. it does not have to condition
                try:
                    condition, newvalue = cAndS
                except TypeError:
                    top = self.stateReg(cAndS)
                    continue
                top = []

            else:
                condition, newvalue = cAndS

            # building decision tree
            top = \
                If(condition,
                   self.stateReg(newvalue)
                ).Else(
                    top
                )
        if stateFrom is None:
            return Switch.Default(self, top)
        else:
            return Switch.Case(self, stateFrom, top)

    def Default(self, *condAndNextState):
        d = self.Trans(None, *condAndNextState)
        d.stateReg = self.stateReg
        return d


# variadic operator functions
And = _mkOp(and_)
Add = _mkOp(add)
Or = _mkOp(or_)
Xor = _mkOp(xor)  # :note: xor is bitwise !=
Xnor = _mkOp(eq)  # :note: xnor is bitwise ==
Concat = _mkOp(concatFn)


def ror(sig:Union[RtlSignalBase, HConst], howMany: int) -> RtlSignalBase:
    "Rotate right"
    if sig._dtype.bit_length() == 1:
        return sig

    if isinstance(howMany, int):
        return sig[howMany:]._concat(sig[:howMany])
    elif isinstance(howMany, HConst):
        return ror(sig, int(howMany))
    else:
        t = howMany._dtype
        if not isinstance(t, HBits) or t.signed:
            raise NotImplementedError(t)
        res = sig
        for i in range(1, t.domain_size() - 1):
            res = howMany._eq(i)._ternary(ror(sig, i), res)
        return  res


def rol(sig:Union[RtlSignalBase, HConst], howMany:Union[RtlSignalBase, int]) -> RtlSignalBase:
    "Rotate left"
    if isinstance(howMany, int):
        width = sig._dtype.bit_length()
        if width == 1:
            return sig
        return sig[(width - howMany):]._concat(sig[:(width - howMany)])
    elif isinstance(howMany, HConst):
        return rol(sig, int(howMany))
    else:
        t = howMany._dtype
        if not isinstance(t, HBits) or t.signed:
            raise NotImplementedError(t)
        res = sig
        for i in range(1, t.domain_size() - 1):
            res = howMany._eq(i)._ternary(rol(sig, i), res)
        return  res


def replicate(n:int, v:Union[RtlSignalBase, HConst]):
    assert n > 0, n
    return Concat(*(v for _ in range(n)))


def segment_get(n:Union[RtlSignalBase, HConst],
                segmentWidth:int,
                segmentIndex:Union[RtlSignalBase, HConst, int]):
    """
    This function gets bits from bit vector as if it was an array of items of "segmentWidth" bits
    """
    return n[segmentWidth * (segmentIndex + 1): segmentWidth * segmentIndex]


def split_to_segments(n:Union[RtlSignalBase, HConst], maxSegmentWidth:int, allowLastToBeSmaller=False, extendLast=False):
    """
    Split bit vector to a segments of up to maxSegmentWidth bits, lower bits first.
    """
    offset = 0
    segments = []
    width = n._dtype.bit_length()
    if not allowLastToBeSmaller and not extendLast:
        assert width % maxSegmentWidth == 0, (width, maxSegmentWidth)

    while True:
        end = min(offset + maxSegmentWidth, width)
        segments.append(n[end:offset])
        if end == width:
            if extendLast and end != offset + maxSegmentWidth:
                segments[-1] = segments[-1]._ext(maxSegmentWidth)
            break
        offset = end
    return segments


1	from operator import and_, or_, xor, add, eq	1✔
2	from types import GeneratorType	1✔
3	from typing import Union, Sequence, Optional, Tuple	1✔
4
5	from hdlConvertorAst.to.hdlUtils import iter_with_last	1✔
6	from hwt.code_utils import _mkOp, _HwIOToRtlSignal	1✔
7	from hwt.hdl.const import HConst	1✔
8	from hwt.hdl.operatorDefs import concatFn	1✔
9	from hwt.hdl.statements.codeBlockContainer import HdlStmCodeBlockContainer	1✔
10	from hwt.hdl.statements.ifContainter import IfContainer	1✔
11	from hwt.hdl.statements.statement import HwtSyntaxError, HdlStatement	1✔
12	from hwt.hdl.statements.switchContainer import SwitchContainer	1✔
13	from hwt.hdl.statements.utils.listOfHdlStatements import ListOfHdlStatement	1✔
14	from hwt.hdl.types.bits import HBits	1✔
15	from hwt.hdl.types.enum import HEnum	1✔
16	from hwt.hdl.types.typeCast import toHVal	1✔
17	from hwt.mainBases import HwIOBase, HwModuleBase	1✔
18	from hwt.mainBases import RtlSignalBase	1✔
19	from hwt.math import log2ceil	1✔
20	from hwt.pyUtils.arrayQuery import arr_any	1✔
21	from hwt.synthesizer.rtlLevel.rtlSignalWalkers import \	1✔
22	discoverEventDependency
23
24
25	class CodeBlock(HdlStmCodeBlockContainer):	1✔
26	"""
27	Container for list of statements
28	"""
29
30	def __init__(self, *statements: Sequence[HdlStatement]):	1✔
31	super(CodeBlock, self).__init__()	1✔
32	self._register_stements(statements, self.statements)	1✔
33	self.rank = sum(map(lambda s: s.rank, statements))	1✔
34
35	if self._outputs:	1!
36	ctx = self._get_rtl_context()	1✔
37	ctx.statements.add(self)	1✔
38
39
40	class If(IfContainer):	1✔
41	"""
42	If statement generator
43	"""
44
45	def __init__(self, cond: Union[RtlSignalBase, HwIOBase], *statements: Sequence[HdlStatement]):	1✔
46	"""
47	:param cond: condition in if statement
48	:param statements: list of statements which should be active
49	if condition is met
50	"""
51	cond_sig = _HwIOToRtlSignal(cond)	1✔
52	if not isinstance(cond_sig, RtlSignalBase):	1!
53	raise HwtSyntaxError("Condition is not signal, it is not certain"	×
54	" if this is an error or desire ", cond_sig)
55
56	assert cond_sig._dtype.bit_length() == 1, cond_sig	1✔
57	super(If, self).__init__(cond_sig)	1✔
58	self.rank = 1	1✔
59	self._inputs.append(cond_sig)	1✔
60	cond_sig._rtlEndpoints.append(self)	1✔
61
62	ev_dep = arr_any(discoverEventDependency(cond_sig), lambda x: True)	1✔
63	self._event_dependent_from_branch = 0 if ev_dep else None	1✔
64
65	self._register_stements(statements, self.ifTrue)	1✔
66	self._get_rtl_context().statements.add(self)	1✔
67
68	def Elif(self, cond: Union[RtlSignalBase, HwIOBase], *statements: Sequence[HdlStatement]):	1✔
69	assert self.parentStm is None	1✔
70	self.rank += 1	1✔
71	cond_sig = _HwIOToRtlSignal(cond)	1✔
72
73	assert cond_sig._dtype.bit_length() == 1, cond_sig	1✔
74	ev_dep = arr_any(discoverEventDependency(cond_sig), lambda x: True)	1✔
75	self._event_dependent_from_branch = len(self.elIfs) + 1 if ev_dep else None	1✔
76
77	self._inputs.append(cond_sig)	1✔
78	cond_sig._rtlEndpoints.append(self)	1✔
79
80	stms = ListOfHdlStatement()	1✔
81	self.elIfs.append((cond_sig, stms))	1✔
82	self._register_stements(statements, stms)	1✔
83
84	return self	1✔
85
86	def Else(self, *statements: Sequence[HdlStatement]):	1✔
87	assert self.parentStm is None	1✔
88	if self.ifFalse is not None:	1!
89	raise HwtSyntaxError(	×
90	"Else on this if-then-else statement was already used")
91
92	self.rank += 1	1✔
93
94	self.ifFalse = ListOfHdlStatement()	1✔
95	self._register_stements(statements, self.ifFalse)	1✔
96	return self	1✔
97
98
99	class Switch(SwitchContainer):	1✔
100	"""
101	Switch statement generator
102	"""
103
104	def __init__(self, switchOn: Union[RtlSignalBase, HwIOBase]):	1✔
105	switchOn = _HwIOToRtlSignal(switchOn)	1✔
106	if not isinstance(switchOn, RtlSignalBase):	1!
107	raise HwtSyntaxError("Select is not signal, it is not certain"	×
108	" if this is an error or desire")
109	if arr_any(discoverEventDependency(switchOn), lambda x: True):	1!
110	raise HwtSyntaxError("Can not switch on result of event operator")	×
111
112	super(Switch, self).__init__(switchOn, [])	1✔
113	switchOn._rtlCtx.statements.add(self)	1✔
114	self._inputs.append(switchOn)	1✔
115	switchOn._rtlEndpoints.append(self)	1✔
116
117	def add_cases(self, tupesValStms: Sequence[Tuple[Union[HConst, int], Sequence[HdlStatement]]]):	1✔
118	"""
119	Add multiple case statements from iterable of tuples
120	(caseVal, statements)
121	"""
122	s = self	1✔
123	for val, statements in tupesValStms:	1✔
124	s = s.Case(val, statements)	1✔
125	return s	1✔
126
127	def Case(self, caseVal: Union[HConst, int], *statements: Sequence[HdlStatement]):	1✔
128	"c-like case of switch statement"
129	assert self.parentStm is None	1✔
130	caseVal = toHVal(caseVal, self.switchOn._dtype)	1✔
131
132	assert isinstance(caseVal, HConst), caseVal	1✔
133	assert caseVal._is_full_valid(), "Cmp with invalid value"	1✔
134	assert caseVal not in self._case_value_index, (	1✔
135	"Switch statement already has case for value ", caseVal)
136
137	self.rank += 1	1✔
138	stms = ListOfHdlStatement()	1✔
139	self._case_value_index[caseVal] = len(self.cases)	1✔
140	self.cases.append((caseVal, stms))	1✔
141	self._register_stements(statements, stms)	1✔
142
143	return self	1✔
144
145	def Default(self, *statements: Sequence[HdlStatement]):	1✔
146	"""c-like default of switch statement
147	"""
148	assert self.parentStm is None	1✔
149	self.rank += 1	1✔
150	self.default = ListOfHdlStatement()	1✔
151	self._register_stements(statements, self.default)	1✔
152	return self	1✔
153
154
155	def SwitchLogic(cases: Sequence[Tuple[Union[RtlSignalBase, HwIOBase, HConst, bool], Sequence[HdlStatement]]],	1✔
156	default: Optional[Sequence[HdlStatement]]=None):
157	"""
158	Generate if tree for cases like (syntax sugar for large generated elifs)
159
160	..code-block:: python
161	if cond0:
162	statements0
163	elif cond1:
164	statements1
165	else:
166	default
167
168	:param case: iterable of tuples (condition, statements)
169	:param default: default statements
170	"""
171	assigTop = None	1✔
172	hasElse = False	1✔
173	for last, (cond, statements) in iter_with_last(cases):	1✔
174	if isinstance(cond, (RtlSignalBase, HwIOBase)):	1✔
175	if assigTop is None:	1✔
176	assigTop = If(cond,	1✔
177	statements
178	)
179	else:
180	assigTop = assigTop.Elif(cond, statements)	1✔
181	else:
182	if cond:	1!
183	if assigTop is None:	1!
184	assigTop = statements	1✔
185	else:
186	assigTop.Else(statements)	×
187	hasElse = True	×
188
189	if last or isinstance(cases, GeneratorType):	1!
190	# allow True as a condition for default
191	break	1✔
192
193	raise HwtSyntaxError("Condition is not a signal, it is not certain"	×
194	" if this is an error or desire ", cond, cases)
195
196	if assigTop is None:	1✔
197	if default is None:	1!
198	return []	×
199	else:
200	return default	1✔
201	else:
202	if hasElse:	1!
203	return assigTop	×
204	elif default is not None:	1✔
205	assigTop = assigTop.Else(default)	1✔
206
207	return assigTop	1✔
208
209
210	def In(sigOrConst: Union[RtlSignalBase, HwIOBase, HConst], iterable: Sequence[Union[RtlSignalBase, HwIOBase, HConst]]):	1✔
211	"""
212	HDL convertible "in" operator, check if any of items
213	in "iterable" equals "sigOrConst"
214	"""
215	res = None	1✔
216	for i in iterable:	1✔
217	i = toHVal(i)	1✔
218	if res is None:	1✔
219	res = sigOrConst._eq(i)	1✔
220	else:
221	res = res \| sigOrConst._eq(i)	1✔
222
223	assert res is not None, "argument iterable is empty"	1✔
224	return res	1✔
225
226
227	def StaticForEach(parentModule: HwModuleBase, items, bodyFn, name=""):	1✔
228	"""
229	Generate for loop for static items
230
231	:param parentModule: HwModule where this code should be instantiated
232	:param items: items which this "for" iterating on
233	:param bodyFn: function which fn(item, index) or fn(item)
234	returns (statementList, ack).
235	It's content is performed in every iteration.
236	When ack is high loop will fall to next iteration
237	"""
238
239	items = list(items)	1✔
240	itemsCnt = len(items)	1✔
241	if itemsCnt == 0:	1!
242	# if there are no items there is nothing to generate
243	return []	×
244	elif itemsCnt == 1:	1✔
245	# if there is only one item do not generate counter logic generate
246	return bodyFn(items[0], 0)	1✔
247	else:
248	# if there is multiple items we have to generate counter logic
249	index = parentModule._reg(name + "for_index",	1✔
250	HBits(log2ceil(itemsCnt + 1), signed=False),
251	def_val=0)
252	ackSig = parentModule._sig(name + "for_ack")	1✔
253
254	statementLists = []	1✔
255	for i, (statementList, ack) in [(i, bodyFn(item, i))	1✔
256	for i, item in enumerate(items)]:
257	statementLists.append(statementList + [(ackSig(ack)), ])	1✔
258
259	If(ackSig,	1✔
260	If(index._eq(itemsCnt - 1),
261	index(0)
262	).Else(
263	index(index + 1)
264	)
265	)
266
267	return Switch(index)\	1✔
268	.add_cases(
269	enumerate(statementLists)
270	).Default(
271	bodyFn(items[0], 0)[0],
272	ackSig(True)
273	)
274
275
276	class FsmBuilder(Switch):	1✔
277	"""
278	A syntax sugar which automatically construct the state transition switch and state register
279
280	:ivar ~.stateReg: register with state
281	"""
282
283	def __init__(self, parentModule: HwModuleBase, stateT, stateRegName="st"):	1✔
284	"""
285	:param parentModule: parent HwModule where FSM should be builded
286	:param stateT: enum type of state
287	:param stateRegName: name of register where sate is stored
288	"""
289	if isinstance(stateT, HEnum):	1!
290	beginVal = stateT.from_py(stateT._allValues[0])	1✔
291	else:
292	beginVal = 0	×
293
294	self.stateReg = parentModule._reg(stateRegName, stateT, beginVal)	1✔
295	Switch.__init__(self, self.stateReg)	1✔
296
297	def Trans(self, stateFrom, *condAndNextState):	1✔
298	"""
299	:param stateFrom: apply when FSM is in this state
300	:param condAndNextState: tuples (condition, newState),
301	last does not to have condition
302
303	:attention: transitions has priority, first has the biggest
304	:attention: if stateFrom is None it is evaluated as default
305	"""
306	top = []	1✔
307	last = True	1✔
308
309	for cAndS in reversed(condAndNextState):	1✔
310	if last is True:	1✔
311	last = False	1✔
312	# if this is last trans. it does not have to condition
313	try:	1✔
314	condition, newvalue = cAndS	1✔
315	except TypeError:	1✔
316	top = self.stateReg(cAndS)	1✔
317	continue	1✔
318	top = []	1✔
319
320	else:
321	condition, newvalue = cAndS	1✔
322
323	# building decision tree
324	top = \	1✔
325	If(condition,
326	self.stateReg(newvalue)
327	).Else(
328	top
329	)
330	if stateFrom is None:	1!
331	return Switch.Default(self, top)	×
332	else:
333	return Switch.Case(self, stateFrom, top)	1✔
334
335	def Default(self, *condAndNextState):	1✔
336	d = self.Trans(None, *condAndNextState)	×
337	d.stateReg = self.stateReg	×
338	return d	×
339
340
341	# variadic operator functions
342	And = _mkOp(and_)	1✔
343	Add = _mkOp(add)	1✔
344	Or = _mkOp(or_)	1✔
345	Xor = _mkOp(xor) # :note: xor is bitwise !=	1✔
346	Xnor = _mkOp(eq) # :note: xnor is bitwise ==	1✔
347	Concat = _mkOp(concatFn)	1✔
348
349
350	def ror(sig:Union[RtlSignalBase, HConst], howMany: int) -> RtlSignalBase:	1✔
351	"Rotate right"
352	if sig._dtype.bit_length() == 1:	1✔
353	return sig	1✔
354
355	if isinstance(howMany, int):	1!
356	return sig[howMany:]._concat(sig[:howMany])	1✔
357	elif isinstance(howMany, HConst):	×
358	return ror(sig, int(howMany))	×
359	else:
360	t = howMany._dtype	×
361	if not isinstance(t, HBits) or t.signed:	×
362	raise NotImplementedError(t)
363	res = sig	×
364	for i in range(1, t.domain_size() - 1):	×
365	res = howMany._eq(i)._ternary(ror(sig, i), res)	×
366	return res	×
367
368
369	def rol(sig:Union[RtlSignalBase, HConst], howMany:Union[RtlSignalBase, int]) -> RtlSignalBase:	1✔
370	"Rotate left"
371	if isinstance(howMany, int):	1!
372	width = sig._dtype.bit_length()	1✔
373	if width == 1:	1!
374	return sig	×
375	return sig[(width - howMany):]._concat(sig[:(width - howMany)])	1✔
376	elif isinstance(howMany, HConst):	×
377	return rol(sig, int(howMany))	×
378	else:
379	t = howMany._dtype	×
380	if not isinstance(t, HBits) or t.signed:	×
381	raise NotImplementedError(t)
382	res = sig	×
383	for i in range(1, t.domain_size() - 1):	×
384	res = howMany._eq(i)._ternary(rol(sig, i), res)	×
385	return res	×
386
387
388	def replicate(n:int, v:Union[RtlSignalBase, HConst]):	1✔
389	assert n > 0, n	1✔
390	return Concat(*(v for _ in range(n)))	1✔
391
392
393	def segment_get(n:Union[RtlSignalBase, HConst],	1✔
394	segmentWidth:int,
395	segmentIndex:Union[RtlSignalBase, HConst, int]):
396	"""
397	This function gets bits from bit vector as if it was an array of items of "segmentWidth" bits
398	"""
399	return n[segmentWidth * (segmentIndex + 1): segmentWidth * segmentIndex]	×
400
401
402	def split_to_segments(n:Union[RtlSignalBase, HConst], maxSegmentWidth:int, allowLastToBeSmaller=False, extendLast=False):	1✔
403	"""
404	Split bit vector to a segments of up to maxSegmentWidth bits, lower bits first.
405	"""
406	offset = 0	×
407	segments = []	×
408	width = n._dtype.bit_length()	×
409	if not allowLastToBeSmaller and not extendLast:	×
410	assert width % maxSegmentWidth == 0, (width, maxSegmentWidth)	×
411
412	while True:	×
413	end = min(offset + maxSegmentWidth, width)	×
414	segments.append(n[end:offset])	×
415	if end == width:	×
416	if extendLast and end != offset + maxSegmentWidth:	×
417	segments[-1] = segments[-1]._ext(maxSegmentWidth)	×
418	break	×
419	offset = end	×
420	return segments	×
421

Nic30 / hwt / 8b945dd2-6cbf-43b3-be54-881b32d4f5e4

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