cfelton / rhea / 421

421

Pull #40

travis-ci

web-flow 
Removed a comment and delay()
Pull Request #40: Fixed VHDL conversion via rhea.build.toolflow.convert, added Clock.ticks property, fixed a typo + spacing

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/home/travis/virtualenv/python2.7.9/lib/python2.7/site-packages/rhea/system/clock.py


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