10799156310

Committed 10 Sep 2024 07:17PM UTC coverage: 50.419% (+4.9%) from 45.564%

Build # 10799156310

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SamboyCoding

Commit Message

More tests for #22 - SIMD and load/store mem tags

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30.26

/Disarm/InternalDisassembly/Arm64ScalarAdvancedSimd.cs

﻿namespace Disarm.InternalDisassembly;

//Advanced SIMD family where op0 is 01x1
internal static class Arm64ScalarAdvancedSimd
{
    public static Arm64Instruction Disassemble(uint instruction)
    {
        var op1 = (instruction >> 23) & 0b11; //Bits 23-24
        var op2 = (instruction >> 19) & 0b1111; //Bits 19-22
        var op3 = (instruction >> 10) & 0b1_1111_1111; //Bits 10-18

        if (op1 == 0 && (op2 >> 2) == 0 && op3.TestPattern(0b000100001, 0b1))
            return Copy(instruction);

        if (op1 is 0b10 or 0b11)
        {
            if (op3.TestBit(0))
            {
                if (op1.TestBit(0))
                    //Op1 11 and op3 ends with a 1
                    throw new Arm64UndefinedInstructionException("Advanced SIMD (scalar): Unallocated");

                return ShiftByImmediate(instruction);
            }

            //Scalar x indexed element
            return ScalarXIndexedElement(instruction);
        }

        //This leaves the largest group, op1 == 0b0x
        //Switch by op2 first, where we can:

        if (op2 == 0b1111)
        {
            if (!op3.TestPattern(0b110000011, 0b10))
                throw new Arm64UndefinedInstructionException("Advanced SIMD (scalar): Unallocated");

            return TwoRegisterMiscFp16(instruction);
        }

        if (op2.TestBit(2))
        {
            //x1xx
            //Check to exclude x100 and x110 first
            if (op2.TestPattern(0b0111, 0b0100) && op3.TestPattern(0b110000011, 0b10))
                return TwoRegisterMisc(instruction);

            if (op2.TestPattern(0b0111, 0b0110) && op3.TestPattern(0b110000011, 0b10))
                return Pairwise(instruction);

            //Remaining x1xx
            if (op3.TestPattern(0b11, 0))
                return ThreeDifferent(instruction);

            if (op3.TestBit(0))
                return ThreeSame(instruction);

            throw new Arm64UndefinedInstructionException($"Advanced SIMD (scalar): Unallocated x1xx family: op2 = 0x{op2:X2}, op3 = {op3:X3}");
        }

        if (op2.TestPattern(0b1100, 0b1000) && op3.TestPattern(0b000110001, 1))
            return ThreeSameFp16(instruction);

        if (op2.TestPattern(0b0100, 0) && op3.TestPattern(0b000100001))
            return ThreeSameExtra(instruction);

        throw new Arm64UndefinedInstructionException($"Advanced SIMD (scalar): Unallocated fall-through, op1 = 0x{op1:X2}, op2 = 0x{op2:X2}, op3 = {op3:X3}");
    }

    public static Arm64Instruction Copy(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.SimdScalarRegisterToRegister, 
        };
    }

    public static Arm64Instruction ShiftByImmediate(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath
        };
    }

    public static Arm64Instruction ScalarXIndexedElement(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,
        };
    }

    public static Arm64Instruction TwoRegisterMiscFp16(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.Unspecified, //Could be comparison, math, conversion, or general data processing
        };
    }

    public static Arm64Instruction TwoRegisterMisc(uint instruction)
    {
        var uFlag = instruction.TestBit(29);
        var size = (instruction >> 22) & 0b11; //Bits 22-23
        var opcode = (instruction >> 12) & 0b1_1111; //Bits 12-16
        var rn = (int) (instruction >> 5) & 0b1_1111; //Bits 5-9
        var rd = (int) instruction & 0b1_1111; //Bits 0-4

        var sz = size.TestBit(0);
        
        //This is almost excessively miscellaneous.
        //Almost everything here has to be handled case-by-case.

        Arm64Register baseReg;
        Arm64Mnemonic mnemonic;
        Arm64MnemonicCategory category;

        switch (opcode)
        {
            case 0b11101 when !uFlag && size is 0b00 or 0b01:
                baseReg = sz ? Arm64Register.D0 : Arm64Register.S0; //32 << sz
                mnemonic = Arm64Mnemonic.SCVTF;
                category = Arm64MnemonicCategory.SimdScalarConversion;
                break;
            default:
                return new()
                {
                    Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
                    MnemonicCategory = Arm64MnemonicCategory.Unspecified, 
                };
        }

        var regD = baseReg + rd;
        var regN = baseReg + rn;

        return new()
        {
            Mnemonic = mnemonic,
            Op0Kind = Arm64OperandKind.Register,
            Op1Kind = Arm64OperandKind.Register,
            Op0Reg = regD,
            Op1Reg = regN,
            MnemonicCategory = category,
        };
    }
    
    public static Arm64Instruction Pairwise(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath, 
        };
    }

    public static Arm64Instruction ThreeDifferent(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath, 
        };
    }

    //"Advanced SIMD Scalar Three Same" derived from C4-587 
    //Note this is NOT the "Advanced SIMD Three Same" - that's in Adm64NonScalarAdvancedSimd.AdvancedSimdThreeSame
    public static Arm64Instruction ThreeSame(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath, 
        };
    }

    public static Arm64Instruction ThreeSameFp16(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.Unspecified, //Scalar or math 
        };
    }

    public static Arm64Instruction ThreeSameExtra(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,
        };
    }
}

1	namespace Disarm.InternalDisassembly;
2
3	//Advanced SIMD family where op0 is 01x1
4	internal static class Arm64ScalarAdvancedSimd
5	{
6	public static Arm64Instruction Disassemble(uint instruction)
7	{
8	var op1 = (instruction >> 23) & 0b11; //Bits 23-24	1✔
9	var op2 = (instruction >> 19) & 0b1111; //Bits 19-22	1✔
10	var op3 = (instruction >> 10) & 0b1_1111_1111; //Bits 10-18	1✔
11
12	if (op1 == 0 && (op2 >> 2) == 0 && op3.TestPattern(0b000100001, 0b1))	1!
13	return Copy(instruction);	×
14
15	if (op1 is 0b10 or 0b11)	1!
16	{
17	if (op3.TestBit(0))	×
18	{
19	if (op1.TestBit(0))	×
20	//Op1 11 and op3 ends with a 1
21	throw new Arm64UndefinedInstructionException("Advanced SIMD (scalar): Unallocated");	×
22
23	return ShiftByImmediate(instruction);	×
24	}
25
26	//Scalar x indexed element
27	return ScalarXIndexedElement(instruction);	×
28	}
29
30	//This leaves the largest group, op1 == 0b0x
31	//Switch by op2 first, where we can:
32
33	if (op2 == 0b1111)	1!
34	{
35	if (!op3.TestPattern(0b110000011, 0b10))	×
36	throw new Arm64UndefinedInstructionException("Advanced SIMD (scalar): Unallocated");	×
37
38	return TwoRegisterMiscFp16(instruction);	×
39	}
40
41	if (op2.TestBit(2))	1!
42	{
43	//x1xx
44	//Check to exclude x100 and x110 first
45	if (op2.TestPattern(0b0111, 0b0100) && op3.TestPattern(0b110000011, 0b10))	1!
46	return TwoRegisterMisc(instruction);	1✔
47
48	if (op2.TestPattern(0b0111, 0b0110) && op3.TestPattern(0b110000011, 0b10))	×
49	return Pairwise(instruction);	×
50
51	//Remaining x1xx
52	if (op3.TestPattern(0b11, 0))	×
53	return ThreeDifferent(instruction);	×
54
55	if (op3.TestBit(0))	×
56	return ThreeSame(instruction);	×
57
58	throw new Arm64UndefinedInstructionException($"Advanced SIMD (scalar): Unallocated x1xx family: op2 = 0x{op2:X2}, op3 = {op3:X3}");	×
59	}
60
61	if (op2.TestPattern(0b1100, 0b1000) && op3.TestPattern(0b000110001, 1))	×
62	return ThreeSameFp16(instruction);	×
63
64	if (op2.TestPattern(0b0100, 0) && op3.TestPattern(0b000100001))	×
65	return ThreeSameExtra(instruction);	×
66
67	throw new Arm64UndefinedInstructionException($"Advanced SIMD (scalar): Unallocated fall-through, op1 = 0x{op1:X2}, op2 = 0x{op2:X2}, op3 = {op3:X3}");	×
68	}
69
70	public static Arm64Instruction Copy(uint instruction)
71	{
72	return new()	×
73	{	×
74	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
75	MnemonicCategory = Arm64MnemonicCategory.SimdScalarRegisterToRegister,	×
76	};	×
77	}
78
79	public static Arm64Instruction ShiftByImmediate(uint instruction)
80	{
81	return new()	×
82	{	×
83	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
84	MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath	×
85	};	×
86	}
87
88	public static Arm64Instruction ScalarXIndexedElement(uint instruction)
89	{
90	return new()	×
91	{	×
92	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
93	MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,	×
94	};	×
95	}
96
97	public static Arm64Instruction TwoRegisterMiscFp16(uint instruction)
98	{
99	return new()	×
100	{	×
101	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
102	MnemonicCategory = Arm64MnemonicCategory.Unspecified, //Could be comparison, math, conversion, or general data processing	×
103	};	×
104	}
105
106	public static Arm64Instruction TwoRegisterMisc(uint instruction)
107	{
108	var uFlag = instruction.TestBit(29);	1✔
109	var size = (instruction >> 22) & 0b11; //Bits 22-23	1✔
110	var opcode = (instruction >> 12) & 0b1_1111; //Bits 12-16	1✔
111	var rn = (int) (instruction >> 5) & 0b1_1111; //Bits 5-9	1✔
112	var rd = (int) instruction & 0b1_1111; //Bits 0-4	1✔
113
114	var sz = size.TestBit(0);	1!
115
116	//This is almost excessively miscellaneous.
117	//Almost everything here has to be handled case-by-case.
118
119	Arm64Register baseReg;
120	Arm64Mnemonic mnemonic;
121	Arm64MnemonicCategory category;
122
123	switch (opcode)
124	{
125	case 0b11101 when !uFlag && size is 0b00 or 0b01:	1!
126	baseReg = sz ? Arm64Register.D0 : Arm64Register.S0; //32 << sz	1!
127	mnemonic = Arm64Mnemonic.SCVTF;	1✔
128	category = Arm64MnemonicCategory.SimdScalarConversion;	1✔
129	break;	1✔
130	default:
131	return new()	×
132	{	×
133	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
134	MnemonicCategory = Arm64MnemonicCategory.Unspecified,	×
135	};	×
136	}
137
138	var regD = baseReg + rd;	1✔
139	var regN = baseReg + rn;	1✔
140
141	return new()	1✔
142	{	1✔
143	Mnemonic = mnemonic,	1✔
144	Op0Kind = Arm64OperandKind.Register,	1✔
145	Op1Kind = Arm64OperandKind.Register,	1✔
146	Op0Reg = regD,	1✔
147	Op1Reg = regN,	1✔
148	MnemonicCategory = category,	1✔
149	};	1✔
150	}
151
152	public static Arm64Instruction Pairwise(uint instruction)
153	{
154	return new()	×
155	{	×
156	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
157	MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,	×
158	};	×
159	}
160
161	public static Arm64Instruction ThreeDifferent(uint instruction)
162	{
163	return new()	×
164	{	×
165	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
166	MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,	×
167	};	×
168	}
169
170	//"Advanced SIMD Scalar Three Same" derived from C4-587
171	//Note this is NOT the "Advanced SIMD Three Same" - that's in Adm64NonScalarAdvancedSimd.AdvancedSimdThreeSame
172	public static Arm64Instruction ThreeSame(uint instruction)
173	{
174	return new()	×
175	{	×
NEW 176	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
NEW 177	MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,	×
UNCOV 178	};	×
179	}
180
181	public static Arm64Instruction ThreeSameFp16(uint instruction)
182	{
183	return new()	×
184	{	×
185	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
186	MnemonicCategory = Arm64MnemonicCategory.Unspecified, //Scalar or math	×
187	};	×
188	}
189
190	public static Arm64Instruction ThreeSameExtra(uint instruction)
191	{
192	return new()	×
193	{	×
194	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
195	MnemonicCategory = Arm64MnemonicCategory.SimdScalarMath,	×
196	};	×
197	}
198	}

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