10793329738

Committed 10 Sep 2024 01:19PM UTC coverage: 39.377% (-5.4%) from 44.746%

Build # 10793329738

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Commit Message

Implemented some families (#22)

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731 of 2489 branches covered (29.37%)

Branch coverage included in aggregate %.

163 of 854 new or added lines in 10 files covered. (19.09%)

18 existing lines in 6 files now uncovered.

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90.82

/Disarm/InternalDisassembly/Arm64System.cs

﻿namespace Disarm.InternalDisassembly;

internal static class Arm64System
{
    public static Arm64Instruction WithResult(uint instruction)
    {
        return new()
        {
            Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,
            MnemonicCategory = Arm64MnemonicCategory.System, 
        };
    }

    public static Arm64Instruction General(uint instruction)
    {
        var l = (instruction >> 21) & 1;
        var op1 = (instruction >> 16) & 0b111; // Bits 16-18
        var CRn = (instruction >> 12) & 0b1111; // Bits 12-15
        var CRm = (instruction >> 8) & 0b1111; // Bits 8-11
        var op2 = (instruction >> 5) & 0b111; // Bits 5-7
        var rt = (int)(instruction & 0b11111); // Bits 0-4

        return l == 1
            ? new() // SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>
            {
                Mnemonic = Arm64Mnemonic.SYSL,
                MnemonicCategory = Arm64MnemonicCategory.System, 
                Op0Kind = Arm64OperandKind.Register,
                Op1Kind = Arm64OperandKind.Immediate,
                Op2Kind = Arm64OperandKind.Immediate,
                Op3Kind = Arm64OperandKind.Immediate,
                Op4Kind = Arm64OperandKind.Immediate,
                Op0Reg = Arm64Register.X0 + rt,
                Op1Imm = op1,
                Op2Imm = CRn,
                Op3Imm = CRm,
                Op4Imm = op2
            }
            : new() // SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}
            {
                Mnemonic = Arm64Mnemonic.SYS,
                MnemonicCategory = Arm64MnemonicCategory.System, 
                Op0Kind = Arm64OperandKind.Immediate,
                Op1Kind = Arm64OperandKind.Immediate,
                Op2Kind = Arm64OperandKind.Immediate,
                Op3Kind = Arm64OperandKind.Immediate,
                Op4Kind = Arm64OperandKind.Register,
                Op0Imm = op1,
                Op1Imm = CRn,
                Op2Imm = CRm,
                Op3Imm = op2,
                Op4Reg = Arm64Register.X0 + rt,
            };
    }

    public static Arm64Instruction RegisterMove(uint instruction)
    {
        var l = (instruction >> 21) & 1;
        var op0 = ((instruction >> 19) & 1) + 2;
        var systemregLow = (instruction >> 5) & (1 << 18); // Bits 5-18
        var systemreg = systemregLow | (op0 << 14);
        var rt = (int)(instruction & 0b11111); // Bits 0-4
        
        return l == 0 ? new() // MSR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>
            {
                Mnemonic = Arm64Mnemonic.MSR,
                MnemonicCategory = Arm64MnemonicCategory.System, 
                Op0Kind = Arm64OperandKind.Immediate, // SystemReg,
                Op1Kind = Arm64OperandKind.Register,
                Op0Imm = systemreg,
                Op1Reg = Arm64Register.X0 + rt
            } 
            : new() // MRS <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)
            {
                Mnemonic = Arm64Mnemonic.MRS,
                MnemonicCategory = Arm64MnemonicCategory.System, 
                Op0Kind = Arm64OperandKind.Register,
                Op1Kind = Arm64OperandKind.Immediate, // SystemReg,
                Op0Reg = Arm64Register.X0 + rt,
                Op1Imm = systemreg
            };
    }

    public static Arm64Instruction WithRegisterArgument(uint instruction)
    {
        var CRm = (instruction >> 8) & 0b1111; // Bits 8-11
        if (CRm != 0)
            throw new Arm64UndefinedInstructionException($"Arm64System with register argument: CRm != 0 (CRm: {CRm:X})");

        var op2 = (instruction >> 5) & 0b111;
        var rd = (int)(instruction & 0b11111); // Bits 0-4
        
        return op2 switch
        {
            0b000 => new()
            {
                Mnemonic = Arm64Mnemonic.WFET,
                MnemonicCategory = Arm64MnemonicCategory.System,
                Op0Kind = Arm64OperandKind.Register,
                Op0Reg = Arm64Register.X0 + rd
            },
            0b001 => new()
            {
                Mnemonic = Arm64Mnemonic.WFIT,
                MnemonicCategory = Arm64MnemonicCategory.System,
                Op0Kind = Arm64OperandKind.Register,
                Op0Reg = Arm64Register.X0 + rd
            },
            _ => throw new Arm64UndefinedInstructionException($"Arm64System with register argument: op2 > 0b001 (op2: {op2:X})")
        };
    }
}

1	namespace Disarm.InternalDisassembly;
2
3	internal static class Arm64System
4	{
5	public static Arm64Instruction WithResult(uint instruction)
6	{
7	return new()	×
8	{	×
9	Mnemonic = Arm64Mnemonic.UNIMPLEMENTED,	×
10	MnemonicCategory = Arm64MnemonicCategory.System,	×
11	};	×
12	}
13
14	public static Arm64Instruction General(uint instruction)
15	{
16	var l = (instruction >> 21) & 1;	2✔
17	var op1 = (instruction >> 16) & 0b111; // Bits 16-18	2✔
18	var CRn = (instruction >> 12) & 0b1111; // Bits 12-15	2✔
19	var CRm = (instruction >> 8) & 0b1111; // Bits 8-11	2✔
20	var op2 = (instruction >> 5) & 0b111; // Bits 5-7	2✔
21	var rt = (int)(instruction & 0b11111); // Bits 0-4	2✔
22
23	return l == 1	2✔
24	? new() // SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>	2✔
25	{	2✔
26	Mnemonic = Arm64Mnemonic.SYSL,	2✔
27	MnemonicCategory = Arm64MnemonicCategory.System,	2✔
28	Op0Kind = Arm64OperandKind.Register,	2✔
29	Op1Kind = Arm64OperandKind.Immediate,	2✔
30	Op2Kind = Arm64OperandKind.Immediate,	2✔
31	Op3Kind = Arm64OperandKind.Immediate,	2✔
32	Op4Kind = Arm64OperandKind.Immediate,	2✔
33	Op0Reg = Arm64Register.X0 + rt,	2✔
34	Op1Imm = op1,	2✔
35	Op2Imm = CRn,	2✔
36	Op3Imm = CRm,	2✔
37	Op4Imm = op2	2✔
38	}	2✔
39	: new() // SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}	2✔
40	{	2✔
41	Mnemonic = Arm64Mnemonic.SYS,	2✔
42	MnemonicCategory = Arm64MnemonicCategory.System,	2✔
43	Op0Kind = Arm64OperandKind.Immediate,	2✔
44	Op1Kind = Arm64OperandKind.Immediate,	2✔
45	Op2Kind = Arm64OperandKind.Immediate,	2✔
46	Op3Kind = Arm64OperandKind.Immediate,	2✔
47	Op4Kind = Arm64OperandKind.Register,	2✔
48	Op0Imm = op1,	2✔
49	Op1Imm = CRn,	2✔
50	Op2Imm = CRm,	2✔
51	Op3Imm = op2,	2✔
52	Op4Reg = Arm64Register.X0 + rt,	2✔
53	};	2✔
54	}
55
56	public static Arm64Instruction RegisterMove(uint instruction)
57	{
58	var l = (instruction >> 21) & 1;	2✔
59	var op0 = ((instruction >> 19) & 1) + 2;	2✔
60	var systemregLow = (instruction >> 5) & (1 << 18); // Bits 5-18	2✔
61	var systemreg = systemregLow \| (op0 << 14);	2✔
62	var rt = (int)(instruction & 0b11111); // Bits 0-4	2✔
63
64	return l == 0 ? new() // MSR (<systemreg>\|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>	2✔
65	{	2✔
66	Mnemonic = Arm64Mnemonic.MSR,	2✔
67	MnemonicCategory = Arm64MnemonicCategory.System,	2✔
68	Op0Kind = Arm64OperandKind.Immediate, // SystemReg,	2✔
69	Op1Kind = Arm64OperandKind.Register,	2✔
70	Op0Imm = systemreg,	2✔
71	Op1Reg = Arm64Register.X0 + rt	2✔
72	}	2✔
73	: new() // MRS <Xt>, (<systemreg>\|S<op0>_<op1>_<Cn>_<Cm>_<op2>)	2✔
74	{	2✔
75	Mnemonic = Arm64Mnemonic.MRS,	2✔
76	MnemonicCategory = Arm64MnemonicCategory.System,	2✔
77	Op0Kind = Arm64OperandKind.Register,	2✔
78	Op1Kind = Arm64OperandKind.Immediate, // SystemReg,	2✔
79	Op0Reg = Arm64Register.X0 + rt,	2✔
80	Op1Imm = systemreg	2✔
81	};	2✔
82	}
83
84	public static Arm64Instruction WithRegisterArgument(uint instruction)
85	{
86	var CRm = (instruction >> 8) & 0b1111; // Bits 8-11	2✔
87	if (CRm != 0)	2!
NEW 88	throw new Arm64UndefinedInstructionException($"Arm64System with register argument: CRm != 0 (CRm: {CRm:X})");	×
89
90	var op2 = (instruction >> 5) & 0b111;	2✔
91	var rd = (int)(instruction & 0b11111); // Bits 0-4	2✔
92
93	return op2 switch	2!
94	{	2✔
95	0b000 => new()	1✔
96	{	1✔
97	Mnemonic = Arm64Mnemonic.WFET,	1✔
98	MnemonicCategory = Arm64MnemonicCategory.System,	1✔
99	Op0Kind = Arm64OperandKind.Register,	1✔
100	Op0Reg = Arm64Register.X0 + rd	1✔
101	},	1✔
102	0b001 => new()	1✔
103	{	1✔
104	Mnemonic = Arm64Mnemonic.WFIT,	1✔
105	MnemonicCategory = Arm64MnemonicCategory.System,	1✔
106	Op0Kind = Arm64OperandKind.Register,	1✔
107	Op0Reg = Arm64Register.X0 + rd	1✔
108	},	1✔
NEW 109	_ => throw new Arm64UndefinedInstructionException($"Arm64System with register argument: op2 > 0b001 (op2: {op2:X})")	×
110	};	2✔
111	}
112	}

SamboyCoding / Disarm / 10793329738

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