b469f1f6-6a00-4958-bfb0-f9fbf427a589

Committed 06 Jun 2024 06:38PM UTC coverage: 93.399% (-0.03%) from 93.431%

Build # b469f1f6-6a00-4958-bfb0-f9fbf427a589

Build Type

push

circleci

Committed by

Nic30

Commit Message

docs

Run Details

8040 of 9100 branches covered (88.35%)

39136 of 41902 relevant lines covered (93.4%)

0.93 hits per line

Source File
Press 'n' to go to next uncovered line, 'b' for previous

98.67

/hwtLib/examples/axi/debugbusmonitor.py

#!/usr/bin/env python3arent
# -*- coding: utf-8 -*-

from typing import Dict, Optional

from hwt.hwIOs.std import HwIOClk, HwIORst_n, HwIODataRdVld
from hwt.hwIOs.utils import addClkRstn, propagateClkRstn
from hwt.hwModule import HwModule
from hwt.pyUtils.typingFuture import override
from hwtLib.abstract.debug_bus_monitor import DebugBusMonitor, \
    DebugBusMonitorDataRecord
from hwtLib.amba.axi4Lite import Axi4Lite
from hwtLib.amba.axiLite_comp.endpoint import AxiLiteEndpoint
from hwtLib.handshaked.reg import HandshakedReg


class DebugBusMonitorExampleAxi(HwModule):
    """
    An example how to use :class:`hwtLib.abstract.debug_bus_monitor.DebugBusMonitor`

    .. hwt-autodoc::
    """

    @override
    def hwConfig(self):
        Axi4Lite.hwConfig(self)

    @override
    def hwDeclr(self):
        addClkRstn(self)
        with self._hwParamsShared():
            self.s = Axi4Lite()
        self.din0 = HwIODataRdVld()
        self.dout0 = HwIODataRdVld()._m()
        self.reg = HandshakedReg(HwIODataRdVld)
        self.din1 = HwIODataRdVld()
        self.dout1 = HwIODataRdVld()._m()

        self.other_clk = HwIOClk()
        self.other_clk.FREQ = self.clk.FREQ * 2
        with self._associated(clk=self.other_clk):
            self.other_rst_n = HwIORst_n()
            self.din2 = HwIODataRdVld()
            self.dout2 = HwIODataRdVld()._m()

    @override
    def hwImpl(self):

        # spy on previously generated circuit
        db = DebugBusMonitor(Axi4Lite, AxiLiteEndpoint)
        intf_to_dbg: Dict[HwIODataRdVld, DebugBusMonitorDataRecord] = {}

        def spy_connections(i: HwIODataRdVld):
            """
            * Construct a record in DebugBusMonitor for a specified interface.
            * Link to other visual nodes on connections.
            * Automatically build nodes for visual hierarchy.
            """
            # cdc if the interface ussing a different clock signal
            parent = i._parent
            parents = []
            while parent is not self:
                parents.append(parent)
                parent = parent._parent

            parent_node: Optional[DebugBusMonitorDataRecord] = None
            for o in reversed(parents):
                n = intf_to_dbg.get(o, None)
                if n is None:
                    n = intf_to_dbg[o] = DebugBusMonitorDataRecord(None, o._name, False, False, False)
                    db.monitored_data.append(n)

                if parent_node is not None:
                    parent_node.children.append(n)
                parent_node = n

            cdc = i._getAssociatedClk() is not self.clk
            n0 = db.register(i, cdc=cdc)
            intf_to_dbg[i] = n0
            n1 = db.register(i, name=i._name + "_snapshot",
                        cdc=cdc,
                        trigger=i.vld & i.rd)

            n0.add_link(n1)
            if parent_node is not None:
                parent_node.add_children(n0)
                parent_node.add_children(n1)

            orig_connect = i._connectTo

            def  _connectTo(master, exclude=None, fit=False):
                n0 = intf_to_dbg[master]
                n1 = intf_to_dbg[i]
                n0.add_link(n1)
                return orig_connect(master, exclude=exclude, fit=fit)

            i._connectTo = _connectTo

        for i in [self.din0,
                  self.dout0, self.din1,
                  self.reg.dataIn, self.reg.dataOut,
                  self.dout1,
                  self.din2,
                  self.dout2,
                  ]:
            spy_connections(i)

        # some connections
        self.dout0(self.din0)
        self.reg.dataIn(self.din1)
        self.dout1(self.reg.dataOut)
        self.dout2(self.din2)
        intf_to_dbg[self.reg.dataIn].add_link(intf_to_dbg[self.reg.dataOut])

        # we need to add register for ".s" because otherwise there would be
        # a combinational loop
        # db.register(self.s, add_reg=True)
        # for hwIO in self.s._hwIOs:
        #    db.register(hwIO, name="s_" + hwIO._name + "_snapshot",
        #                trigger=hwIO.valid & hwIO.ready)

        with self._hwParamsShared():
            self.db = db
        db.s(self.s)
        # there we actually connect the monitored interface
        # to the monitor instance
        db.apply_connections()

        propagateClkRstn(self)


if __name__ == '__main__':
    from hwt.synth import to_rtl_str
    
    m = DebugBusMonitorExampleAxi()
    print(to_rtl_str(m))

1	#!/usr/bin/env python3arent
2	# -- coding: utf-8 --
3
4	from typing import Dict, Optional	1✔
5
6	from hwt.hwIOs.std import HwIOClk, HwIORst_n, HwIODataRdVld	1✔
7	from hwt.hwIOs.utils import addClkRstn, propagateClkRstn	1✔
8	from hwt.hwModule import HwModule	1✔
9	from hwt.pyUtils.typingFuture import override	1✔
10	from hwtLib.abstract.debug_bus_monitor import DebugBusMonitor, \	1✔
11	DebugBusMonitorDataRecord
12	from hwtLib.amba.axi4Lite import Axi4Lite	1✔
13	from hwtLib.amba.axiLite_comp.endpoint import AxiLiteEndpoint	1✔
14	from hwtLib.handshaked.reg import HandshakedReg	1✔
15
16
17	class DebugBusMonitorExampleAxi(HwModule):	1✔
18	"""
19	An example how to use :class:`hwtLib.abstract.debug_bus_monitor.DebugBusMonitor`
20
21	.. hwt-autodoc::
22	"""
23
24	@override	1✔
25	def hwConfig(self):	1✔
26	Axi4Lite.hwConfig(self)	1✔
27
28	@override	1✔
29	def hwDeclr(self):	1✔
30	addClkRstn(self)	1✔
31	with self._hwParamsShared():	1✔
32	self.s = Axi4Lite()	1✔
33	self.din0 = HwIODataRdVld()	1✔
34	self.dout0 = HwIODataRdVld()._m()	1✔
35	self.reg = HandshakedReg(HwIODataRdVld)	1✔
36	self.din1 = HwIODataRdVld()	1✔
37	self.dout1 = HwIODataRdVld()._m()	1✔
38
39	self.other_clk = HwIOClk()	1✔
40	self.other_clk.FREQ = self.clk.FREQ * 2	1✔
41	with self._associated(clk=self.other_clk):	1✔
42	self.other_rst_n = HwIORst_n()	1✔
43	self.din2 = HwIODataRdVld()	1✔
44	self.dout2 = HwIODataRdVld()._m()	1✔
45
46	@override	1✔
47	def hwImpl(self):	1✔
48
49	# spy on previously generated circuit
50	db = DebugBusMonitor(Axi4Lite, AxiLiteEndpoint)	1✔
51	intf_to_dbg: Dict[HwIODataRdVld, DebugBusMonitorDataRecord] = {}	1✔
52
53	def spy_connections(i: HwIODataRdVld):	1✔
54	"""
55	* Construct a record in DebugBusMonitor for a specified interface.
56	* Link to other visual nodes on connections.
57	* Automatically build nodes for visual hierarchy.
58	"""
59	# cdc if the interface ussing a different clock signal
60	parent = i._parent	1✔
61	parents = []	1✔
62	while parent is not self:	1✔
63	parents.append(parent)	1✔
64	parent = parent._parent	1✔
65
66	parent_node: Optional[DebugBusMonitorDataRecord] = None	1✔
67	for o in reversed(parents):	1✔
68	n = intf_to_dbg.get(o, None)	1✔
69	if n is None:	1✔
70	n = intf_to_dbg[o] = DebugBusMonitorDataRecord(None, o._name, False, False, False)	1✔
71	db.monitored_data.append(n)	1✔
72
73	if parent_node is not None:	1!
74	parent_node.children.append(n)	×
75	parent_node = n	1✔
76
77	cdc = i._getAssociatedClk() is not self.clk	1✔
78	n0 = db.register(i, cdc=cdc)	1✔
79	intf_to_dbg[i] = n0	1✔
80	n1 = db.register(i, name=i._name + "_snapshot",	1✔
81	cdc=cdc,
82	trigger=i.vld & i.rd)
83
84	n0.add_link(n1)	1✔
85	if parent_node is not None:	1✔
86	parent_node.add_children(n0)	1✔
87	parent_node.add_children(n1)	1✔
88
89	orig_connect = i._connectTo	1✔
90
91	def _connectTo(master, exclude=None, fit=False):	1✔
92	n0 = intf_to_dbg[master]	1✔
93	n1 = intf_to_dbg[i]	1✔
94	n0.add_link(n1)	1✔
95	return orig_connect(master, exclude=exclude, fit=fit)	1✔
96
97	i._connectTo = _connectTo	1✔
98
99	for i in [self.din0,	1✔
100	self.dout0, self.din1,
101	self.reg.dataIn, self.reg.dataOut,
102	self.dout1,
103	self.din2,
104	self.dout2,
105	]:
106	spy_connections(i)	1✔
107
108	# some connections
109	self.dout0(self.din0)	1✔
110	self.reg.dataIn(self.din1)	1✔
111	self.dout1(self.reg.dataOut)	1✔
112	self.dout2(self.din2)	1✔
113	intf_to_dbg[self.reg.dataIn].add_link(intf_to_dbg[self.reg.dataOut])	1✔
114
115	# we need to add register for ".s" because otherwise there would be
116	# a combinational loop
117	# db.register(self.s, add_reg=True)
118	# for hwIO in self.s._hwIOs:
119	# db.register(hwIO, name="s_" + hwIO._name + "_snapshot",
120	# trigger=hwIO.valid & hwIO.ready)
121
122	with self._hwParamsShared():	1✔
123	self.db = db	1✔
124	db.s(self.s)	1✔
125	# there we actually connect the monitored interface
126	# to the monitor instance
127	db.apply_connections()	1✔
128
129	propagateClkRstn(self)	1✔
130
131
132	if __name__ == '__main__':
133	from hwt.synth import to_rtl_str
134
135	m = DebugBusMonitorExampleAxi()
136	print(to_rtl_str(m))

Nic30 / hwtLib / b469f1f6-6a00-4958-bfb0-f9fbf427a589

Source File Press 'n' to go to next uncovered line, 'b' for previous

Source File
Press 'n' to go to next uncovered line, 'b' for previous