b469f1f6-6a00-4958-bfb0-f9fbf427a589

Committed 06 Jun 2024 06:38PM UTC coverage: 93.399% (-0.03%) from 93.431%

Build # b469f1f6-6a00-4958-bfb0-f9fbf427a589

Build Type

push

circleci

Committed by

Nic30

Commit Message

docs

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65.85

/hwtLib/amba/axi_comp/cache/utils.py

from math import ceil

from hwt.code import Concat
from hwt.hdl.types.bits import HBits
from hwt.math import log2ceil
from hwt.pyUtils.typingFuture import override
from hwtLib.commonHwIO.addr_data import HwIOAddrData
from hwtLib.mem.cam import CamMultiPort
from pyMathBitPrecise.bit_utils import apply_set_and_clear


def expand_byte_mask_to_bit_mask(m):
    res = []
    for b in m:
        B = []
        for _ in range(8):
            B.append(b)

        res.append(Concat(*B))

    return Concat(*reversed(res))


def apply_write_with_mask(current_data, new_data, write_mask):
    m = expand_byte_mask_to_bit_mask(write_mask)
    return apply_set_and_clear(current_data, new_data & m, m)


def extend_to_width_multiple_of_8(sig):
    """
    make width of signal modulo 8 equal to 0
    """
    w = sig._dtype.bit_length()
    cosest_multiple_of_8 = ceil((w // 8) / 8) * 8
    if cosest_multiple_of_8 == w:
        return sig
    else:
        return Concat(HBits(cosest_multiple_of_8 - w).from_py(0), sig)


class CamWithReadPort(CamMultiPort):
    """
    Content addressable memory with a read port which can be used
    to read cam array by index

    .. hwt-autodoc::
    """

    @override
    def hwConfig(self):
        CamMultiPort.hwConfig(self)
        self.USE_VLD_BIT = False

    @override
    def hwDeclr(self):
        assert not self.USE_VLD_BIT
        CamMultiPort.hwDeclr(self)
        r = self.read = HwIOAddrData()
        r.ADDR_WIDTH = log2ceil(self.ITEMS - 1)
        r.DATA_WIDTH = self.KEY_WIDTH

    @override
    def hwImpl(self):
        CamMultiPort.hwImpl(self)
        self.read.data(self._mem[self.read.addr])


1	from math import ceil	1✔
2
3	from hwt.code import Concat	1✔
4	from hwt.hdl.types.bits import HBits	1✔
5	from hwt.math import log2ceil	1✔
6	from hwt.pyUtils.typingFuture import override	1✔
7	from hwtLib.commonHwIO.addr_data import HwIOAddrData	1✔
8	from hwtLib.mem.cam import CamMultiPort	1✔
9	from pyMathBitPrecise.bit_utils import apply_set_and_clear	1✔
10
11
12	def expand_byte_mask_to_bit_mask(m):	1✔
13	res = []	×
14	for b in m:	×
15	B = []	×
16	for _ in range(8):	×
17	B.append(b)	×
18
19	res.append(Concat(*B))	×
20
21	return Concat(*reversed(res))	×
22
23
24	def apply_write_with_mask(current_data, new_data, write_mask):	1✔
25	m = expand_byte_mask_to_bit_mask(write_mask)	×
26	return apply_set_and_clear(current_data, new_data & m, m)	×
27
28
29	def extend_to_width_multiple_of_8(sig):	1✔
30	"""
31	make width of signal modulo 8 equal to 0
32	"""
33	w = sig._dtype.bit_length()	×
34	cosest_multiple_of_8 = ceil((w // 8) / 8) * 8	×
35	if cosest_multiple_of_8 == w:	×
36	return sig	×
37	else:
38	return Concat(HBits(cosest_multiple_of_8 - w).from_py(0), sig)	×
39
40
41	class CamWithReadPort(CamMultiPort):	1✔
42	"""
43	Content addressable memory with a read port which can be used
44	to read cam array by index
45
46	.. hwt-autodoc::
47	"""
48
49	@override	1✔
50	def hwConfig(self):	1✔
51	CamMultiPort.hwConfig(self)	1✔
52	self.USE_VLD_BIT = False	1✔
53
54	@override	1✔
55	def hwDeclr(self):	1✔
56	assert not self.USE_VLD_BIT	1✔
57	CamMultiPort.hwDeclr(self)	1✔
58	r = self.read = HwIOAddrData()	1✔
59	r.ADDR_WIDTH = log2ceil(self.ITEMS - 1)	1✔
60	r.DATA_WIDTH = self.KEY_WIDTH	1✔
61
62	@override	1✔
63	def hwImpl(self):	1✔
64	CamMultiPort.hwImpl(self)	1✔
65	self.read.data(self._mem[self.read.addr])	1✔
66

Nic30 / hwtLib / b469f1f6-6a00-4958-bfb0-f9fbf427a589

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