8403568f-6712-4b41-91dc-bea6873decce

Committed 06 Jun 2024 04:48PM UTC coverage: 87.259% (-0.06%) from 87.318%

Build # 8403568f-6712-4b41-91dc-bea6873decce

Build Type

push

circleci

Committed by

Nic30

Commit Message

fix(sim): name for shared submodules

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3598 of 4503 branches covered (79.9%)

Branch coverage included in aggregate %.

1 of 1 new or added line in 1 file covered. (100.0%)

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87.72

/hwt/synthesizer/rtlLevel/netlist.py

from typing import List, Optional, Union, Dict, Set

from hdlConvertorAst.hdlAst._defs import HdlIdDef
from hdlConvertorAst.hdlAst._expr import HdlValueId
from hdlConvertorAst.hdlAst._structural import HdlModuleDec, HdlModuleDef, \
    HdlCompInst
from hwt.code import If
from hwt.constants import NOT_SPECIFIED
from hwt.doc_markers import internal
from hwt.hdl.const import HConst
from hwt.hdl.operatorDefs import HwtOps
from hwt.hdl.statements.codeBlockContainer import HdlStmCodeBlockContainer
from hwt.hdl.statements.statement import HdlStatement
from hwt.hdl.types.defs import BIT
from hwt.hdl.types.hdlType import HdlType
from hwt.hwParam import HwParam
from hwt.mainBases import HwIOBase
from hwt.serializer.utils import HdlStatement_sort_key, RtlSignal_sort_key
from hwt.synthesizer.dummyPlatform import DummyPlatform
from hwt.synthesizer.exceptions import SigLvlConfErr
from hwt.synthesizer.rtlLevel.rtlNetlistPass import RtlNetlistPass
from hwt.synthesizer.rtlLevel.rtlSignal import RtlSignal
from hwt.synthesizer.rtlLevel.rtlSyncSignal import RtlSyncSignal
from hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers import statements_to_HdlStmCodeBlockContainers
from ipCorePackager.constants import DIRECTION


class RtlNetlist():
    """
    Hierarchical container for signals

    :ivar ~.parent: optional parent for debug and late component inspection
    :ivar ~.signals: set of all signals in this context
    :ivar ~.statements: list of all statements which are connected to signals in this context
    :ivar ~.subHwModules: is set of all units in this context
    :ivar ~.hwIOs: initialized in create_HdlModuleDef
    :ivar ~.hwModDec: initialized in create_HdlModuleDec
    :ivar ~.hwModDef: initialized in create_HdlModuleDef
    """

    def __init__(self, parent: Optional["HwModule"]=None):
        self.parent = parent
        self.signals: Set[RtlSignal] = set()
        self.statements: Set[HdlStatement] = set()
        self.subHwModules: Set["HwModule"] = set()
        self.hwIOs: Dict[RtlSignal, DIRECTION] = {}
        self.hwModDec: Optional[HdlModuleDec] = None
        self.hwModDef: Optional[HdlModuleDef] = None

    def sig(self, name: str, dtype=BIT, clk=None, syncRst=None,
            def_val=None, nop_val=NOT_SPECIFIED, nextSig=NOT_SPECIFIED) -> Union[RtlSignal, RtlSyncSignal]:
        """
        Create new signal in this context

        :param clk: clock signal, if specified signal is synthesized
            as RtlSyncSignal
        :param syncRst: synchronous reset signal
        :param def_val: a default value used for reset and initialization
        :param nop_val: a value which is used to drive the signal if there is no other drive
            (used to prevent latches and to specify default values for unconnected signals)
        :param nextSig: the signal which should be used as "next" signal for this register
            if is not specified the new signal is generated. (Next signal holds value which should be in register in next clk.)
        
        """
        _def_val = _try_cast_any_to_HValue(def_val, dtype, True)
        if nop_val is not NOT_SPECIFIED:
            nop_val = _try_cast_any_to_HValue(nop_val, dtype, False)

        if clk is not None:
            if nextSig is not None and isinstance(nextSig, HwIOBase):
                nextSig = nextSig._sig
            s = RtlSyncSignal(self, name, dtype,
                              _def_val if isinstance(_def_val, HConst) else dtype.from_py(None),
                              nop_val,
                              nextSig)
            if syncRst is not None and def_val is None:
                raise SigLvlConfErr(
                    "Probably forgotten default value on sync signal %s", name)
            # dst_resolve_fn is overridden because default assign would assign to the "next" signal
            if syncRst is not None:
                r = If(syncRst._isOn(),
                       s(_def_val, dst_resolve_fn=lambda x: x)
                    ).Else(
                       s(s.next, dst_resolve_fn=lambda x: x)
                    )
            else:
                r = [
                    s(s.next, dst_resolve_fn=lambda x: x)
                ]

            if isinstance(clk, (HwIOBase, RtlSignal)):
                clk_trigger = clk._onRisingEdge()
            else:
                # has to be tuple of (clk_sig, HwtOps.RISING/FALLING_EDGE)
                clk, clk_edge = clk
                if clk_edge is HwtOps.RISING_EDGE:
                    clk_trigger = clk._onRisingEdge()
                elif clk_edge is HwtOps.FALLING_EDGE:
                    clk_trigger = clk._onRisingEdge()
                else:
                    raise ValueError(
                        "Invalid clock edge specification", clk_edge)

            If(clk_trigger,
               r
            )
        else:
            if syncRst:
                raise SigLvlConfErr(
                    f"Signal {name:s} has reset but has no clk")
            if nextSig is not NOT_SPECIFIED:
                raise SigLvlConfErr(
                    f"Signal {name:s} has nextSig which is used for next register value, but has no clock and thus is not a register.")

            assert isinstance(_def_val, HConst) or (isinstance(_def_val, RtlSignal) and _def_val._const), (_def_val, "The default value needs to be constant")
            s = RtlSignal(self, name, dtype, def_val=_def_val, nop_val=nop_val)

        return s

    def create_HdlModuleDec(self, name: str,
                            store_manager: "StoreManager",
                            params: List[HwParam]):
        """
        Generate a module header (entity) for this module
        """
        self.hwModDec = hwModDec = HdlModuleDec()
        hwModDec.name = store_manager.name_scope.checked_name(name, hwModDec)
        ns = store_manager.hierarchy_push(hwModDec)
        # create generics
        for p in sorted(params, key=lambda x: x._name):
            hdl_val = p.get_hdl_value()
            v = HdlIdDef()
            v.origin = p
            # sanitize param name
            v.name = p._name = ns.checked_name(p._name, p)
            v.type = hdl_val._dtype
            v.value = hdl_val
            hwModDec.params.append(v)

        return hwModDec

    def create_HdlModuleDef(self,
                            target_platform: DummyPlatform,
                            store_manager: "StoreManager"):
        """
        Generate a module body (architecture) for this module

        * Resolve name collisions
        * Convert netlist representation to HdlProcesses
        * Remove unconnected
        * Mark visibility of signals
        """
        for optPass in target_platform.beforeHdlArchGeneration:
            optPass: RtlNetlistPass
            optPass.runOnRtlNetlist(self)

        ns = store_manager.name_scope
        mdef = HdlModuleDef()
        mdef.dec = self.hwModDec
        mdef.module_name = HdlValueId(self.hwModDec.name, obj=self.hwModDec)
        mdef.name = "rtl"

        processes = sorted(self.statements, key=HdlStatement_sort_key)
        processes = sorted(statements_to_HdlStmCodeBlockContainers(processes), key=HdlStatement_sort_key)

        # add signals, variables, etc. in architecture
        for s in sorted((s for s in self.signals
                        if not s.hidden and
                        s not in self.hwIOs.keys()),
                        key=RtlSignal_sort_key):
            s: RtlSignal
            assert s.ctx is self, ("RtlSignals in this context must know that they are in this context", s)
            v = HdlIdDef()
            v.origin = s
            v.name = s._name = ns.checked_name(s._name, s)
            v.type = s._dtype
            v.value = s.def_val
            v.is_const = s._const
            mdef.objs.append(v)

        for p in processes:
            p: HdlStmCodeBlockContainer
            p.name = ns.checked_name(p.name, p)

        mdef.objs.extend(processes)
        # instantiate subModules in architecture
        for sm in self.subHwModules:
            ci = HdlCompInst()
            ci.origin = sm
            ci.module_name = HdlValueId(sm._ctx.hwModDec.name, obj=sm._ctx.hwModDec)
            ci.name = HdlValueId(ns.checked_name(sm._name + "_inst", ci), obj=sm)
            hwModDec = sm._ctx.hwModDec

            ci.param_map.extend(hwModDec.params)
            ci.port_map.extend(hwModDec.ports)

            mdef.objs.append(ci)

        self.hwModDef = mdef
        return mdef

    def getDebugScopeName(self):
        scope = []
        p = self.parent
        while p is not None:
            scope.append(p._name)
            try:
                p = p._parent
            except AttributeError:
                break

        return ".".join(reversed(scope))


@internal
def _try_cast_any_to_HValue(v, dtype: HdlType, require_const: bool):
    if isinstance(v, RtlSignal):
        assert not require_const or v._const, \
            "Initial value of signal has to be a constant"
        return v._auto_cast(dtype)
    elif isinstance(v, HConst):
        return v._auto_cast(dtype)
    elif isinstance(v, HwIOBase):
        return v._sig
    else:
        return dtype.from_py(v)

1	from typing import List, Optional, Union, Dict, Set	1✔
2
3	from hdlConvertorAst.hdlAst._defs import HdlIdDef	1✔
4	from hdlConvertorAst.hdlAst._expr import HdlValueId	1✔
5	from hdlConvertorAst.hdlAst._structural import HdlModuleDec, HdlModuleDef, \	1✔
6	HdlCompInst
7	from hwt.code import If	1✔
8	from hwt.constants import NOT_SPECIFIED	1✔
9	from hwt.doc_markers import internal	1✔
10	from hwt.hdl.const import HConst	1✔
11	from hwt.hdl.operatorDefs import HwtOps	1✔
12	from hwt.hdl.statements.codeBlockContainer import HdlStmCodeBlockContainer	1✔
13	from hwt.hdl.statements.statement import HdlStatement	1✔
14	from hwt.hdl.types.defs import BIT	1✔
15	from hwt.hdl.types.hdlType import HdlType	1✔
16	from hwt.hwParam import HwParam	1✔
17	from hwt.mainBases import HwIOBase	1✔
18	from hwt.serializer.utils import HdlStatement_sort_key, RtlSignal_sort_key	1✔
19	from hwt.synthesizer.dummyPlatform import DummyPlatform	1✔
20	from hwt.synthesizer.exceptions import SigLvlConfErr	1✔
21	from hwt.synthesizer.rtlLevel.rtlNetlistPass import RtlNetlistPass	1✔
22	from hwt.synthesizer.rtlLevel.rtlSignal import RtlSignal	1✔
23	from hwt.synthesizer.rtlLevel.rtlSyncSignal import RtlSyncSignal	1✔
24	from hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers import statements_to_HdlStmCodeBlockContainers	1✔
25	from ipCorePackager.constants import DIRECTION	1✔
26
27
28	class RtlNetlist():	1✔
29	"""
30	Hierarchical container for signals
31
32	:ivar ~.parent: optional parent for debug and late component inspection
33	:ivar ~.signals: set of all signals in this context
34	:ivar ~.statements: list of all statements which are connected to signals in this context
35	:ivar ~.subHwModules: is set of all units in this context
36	:ivar ~.hwIOs: initialized in create_HdlModuleDef
37	:ivar ~.hwModDec: initialized in create_HdlModuleDec
38	:ivar ~.hwModDef: initialized in create_HdlModuleDef
39	"""
40
41	def __init__(self, parent: Optional["HwModule"]=None):	1✔
42	self.parent = parent	1✔
43	self.signals: Set[RtlSignal] = set()	1✔
44	self.statements: Set[HdlStatement] = set()	1✔
45	self.subHwModules: Set["HwModule"] = set()	1✔
46	self.hwIOs: Dict[RtlSignal, DIRECTION] = {}	1✔
47	self.hwModDec: Optional[HdlModuleDec] = None	1✔
48	self.hwModDef: Optional[HdlModuleDef] = None	1✔
49
50	def sig(self, name: str, dtype=BIT, clk=None, syncRst=None,	1✔
51	def_val=None, nop_val=NOT_SPECIFIED, nextSig=NOT_SPECIFIED) -> Union[RtlSignal, RtlSyncSignal]:
52	"""
53	Create new signal in this context
54
55	:param clk: clock signal, if specified signal is synthesized
56	as RtlSyncSignal
57	:param syncRst: synchronous reset signal
58	:param def_val: a default value used for reset and initialization
59	:param nop_val: a value which is used to drive the signal if there is no other drive
60	(used to prevent latches and to specify default values for unconnected signals)
61	:param nextSig: the signal which should be used as "next" signal for this register
62	if is not specified the new signal is generated. (Next signal holds value which should be in register in next clk.)
63
64	"""
65	_def_val = _try_cast_any_to_HValue(def_val, dtype, True)	1✔
66	if nop_val is not NOT_SPECIFIED:	1✔
67	nop_val = _try_cast_any_to_HValue(nop_val, dtype, False)	1✔
68
69	if clk is not None:	1✔
70	if nextSig is not None and isinstance(nextSig, HwIOBase):	1!
UNCOV 71	nextSig = nextSig._sig	×
72	s = RtlSyncSignal(self, name, dtype,	1✔
73	_def_val if isinstance(_def_val, HConst) else dtype.from_py(None),
74	nop_val,
75	nextSig)
76	if syncRst is not None and def_val is None:	1!
UNCOV 77	raise SigLvlConfErr(	×
78	"Probably forgotten default value on sync signal %s", name)
79	# dst_resolve_fn is overridden because default assign would assign to the "next" signal
80	if syncRst is not None:	1✔
81	r = If(syncRst._isOn(),	1✔
82	s(_def_val, dst_resolve_fn=lambda x: x)
83	).Else(
84	s(s.next, dst_resolve_fn=lambda x: x)
85	)
86	else:
87	r = [	1✔
88	s(s.next, dst_resolve_fn=lambda x: x)
89	]
90
91	if isinstance(clk, (HwIOBase, RtlSignal)):	1✔
92	clk_trigger = clk._onRisingEdge()	1✔
93	else:
94	# has to be tuple of (clk_sig, HwtOps.RISING/FALLING_EDGE)
95	clk, clk_edge = clk	1✔
96	if clk_edge is HwtOps.RISING_EDGE:	1✔
97	clk_trigger = clk._onRisingEdge()	1✔
98	elif clk_edge is HwtOps.FALLING_EDGE:	1!
99	clk_trigger = clk._onRisingEdge()	1✔
100	else:
UNCOV 101	raise ValueError(	×
102	"Invalid clock edge specification", clk_edge)
103
104	If(clk_trigger,	1✔
105	r
106	)
107	else:
108	if syncRst:	1!
109	raise SigLvlConfErr(	×
110	f"Signal {name:s} has reset but has no clk")
111	if nextSig is not NOT_SPECIFIED:	1!
UNCOV 112	raise SigLvlConfErr(	×
113	f"Signal {name:s} has nextSig which is used for next register value, but has no clock and thus is not a register.")
114
115	assert isinstance(_def_val, HConst) or (isinstance(_def_val, RtlSignal) and _def_val._const), (_def_val, "The default value needs to be constant")	1✔
116	s = RtlSignal(self, name, dtype, def_val=_def_val, nop_val=nop_val)	1✔
117
118	return s	1✔
119
120	def create_HdlModuleDec(self, name: str,	1✔
121	store_manager: "StoreManager",
122	params: List[HwParam]):
123	"""
124	Generate a module header (entity) for this module
125	"""
126	self.hwModDec = hwModDec = HdlModuleDec()	1✔
127	hwModDec.name = store_manager.name_scope.checked_name(name, hwModDec)	1✔
128	ns = store_manager.hierarchy_push(hwModDec)	1✔
129	# create generics
130	for p in sorted(params, key=lambda x: x._name):	1✔
131	hdl_val = p.get_hdl_value()	1✔
132	v = HdlIdDef()	1✔
133	v.origin = p	1✔
134	# sanitize param name
135	v.name = p._name = ns.checked_name(p._name, p)	1✔
136	v.type = hdl_val._dtype	1✔
137	v.value = hdl_val	1✔
138	hwModDec.params.append(v)	1✔
139
140	return hwModDec	1✔
141
142	def create_HdlModuleDef(self,	1✔
143	target_platform: DummyPlatform,
144	store_manager: "StoreManager"):
145	"""
146	Generate a module body (architecture) for this module
147
148	* Resolve name collisions
149	* Convert netlist representation to HdlProcesses
150	* Remove unconnected
151	* Mark visibility of signals
152	"""
153	for optPass in target_platform.beforeHdlArchGeneration:	1✔
154	optPass: RtlNetlistPass
155	optPass.runOnRtlNetlist(self)	1✔
156
157	ns = store_manager.name_scope	1✔
158	mdef = HdlModuleDef()	1✔
159	mdef.dec = self.hwModDec	1✔
160	mdef.module_name = HdlValueId(self.hwModDec.name, obj=self.hwModDec)	1✔
161	mdef.name = "rtl"	1✔
162
163	processes = sorted(self.statements, key=HdlStatement_sort_key)	1✔
164	processes = sorted(statements_to_HdlStmCodeBlockContainers(processes), key=HdlStatement_sort_key)	1✔
165
166	# add signals, variables, etc. in architecture
167	for s in sorted((s for s in self.signals	1✔
168	if not s.hidden and
169	s not in self.hwIOs.keys()),
170	key=RtlSignal_sort_key):
171	s: RtlSignal
172	assert s.ctx is self, ("RtlSignals in this context must know that they are in this context", s)	1✔
173	v = HdlIdDef()	1✔
174	v.origin = s	1✔
175	v.name = s._name = ns.checked_name(s._name, s)	1✔
176	v.type = s._dtype	1✔
177	v.value = s.def_val	1✔
178	v.is_const = s._const	1✔
179	mdef.objs.append(v)	1✔
180
181	for p in processes:	1✔
182	p: HdlStmCodeBlockContainer
183	p.name = ns.checked_name(p.name, p)	1✔
184
185	mdef.objs.extend(processes)	1✔
186	# instantiate subModules in architecture
187	for sm in self.subHwModules:	1✔
188	ci = HdlCompInst()	1✔
189	ci.origin = sm	1✔
190	ci.module_name = HdlValueId(sm._ctx.hwModDec.name, obj=sm._ctx.hwModDec)	1✔
191	ci.name = HdlValueId(ns.checked_name(sm._name + "_inst", ci), obj=sm)	1✔
192	hwModDec = sm._ctx.hwModDec	1✔
193
194	ci.param_map.extend(hwModDec.params)	1✔
195	ci.port_map.extend(hwModDec.ports)	1✔
196
197	mdef.objs.append(ci)	1✔
198
199	self.hwModDef = mdef	1✔
200	return mdef	1✔
201
202	def getDebugScopeName(self):	1✔
203	scope = []	×
UNCOV 204	p = self.parent	×
205	while p is not None:	×
UNCOV 206	scope.append(p._name)	×
UNCOV 207	try:	×
UNCOV 208	p = p._parent	×
UNCOV 209	except AttributeError:	×
UNCOV 210	break	×
211
UNCOV 212	return ".".join(reversed(scope))	×
213
214
215	@internal	1✔
216	def _try_cast_any_to_HValue(v, dtype: HdlType, require_const: bool):	1✔
217	if isinstance(v, RtlSignal):	1✔
218	assert not require_const or v._const, \	1✔
219	"Initial value of signal has to be a constant"
220	return v._auto_cast(dtype)	1✔
221	elif isinstance(v, HConst):	1✔
222	return v._auto_cast(dtype)	1✔
223	elif isinstance(v, HwIOBase):	1✔
224	return v._sig	1✔
225	else:
226	return dtype.from_py(v)	1✔

Nic30 / hwt / 8403568f-6712-4b41-91dc-bea6873decce

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