2be76794-4dd2-4abd-8081-a937932017ea

Committed 09 Apr 2024 11:58AM UTC coverage: 87.565% (+0.004%) from 87.561%

Build # 2be76794-4dd2-4abd-8081-a937932017ea

Build Type

push

circleci

Committed by

Nic30

Commit Message

fix(BitsVal):prevent construction of 1b sig subscr. 0 if subscr. on conc

Run Details

3877 of 4761 branches covered (81.43%)

Branch coverage included in aggregate %.

10 of 10 new or added lines in 1 file covered. (100.0%)

9 existing lines in 1 file now uncovered.

11059 of 12296 relevant lines covered (89.94%)

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76.53

/hwt/synthesizer/interfaceLevel/interfaceUtils/utils.py

from typing import Union

from hwt.hdl.constants import DIRECTION
from hwt.hdl.types.bits import Bits
from hwt.hdl.types.bitsVal import BitsVal
from hwt.synthesizer.interfaceLevel.mainBases import InterfaceBase
from hwt.synthesizer.rtlLevel.mainBases import RtlSignalBase


class NotSpecified(Exception):
    """
    This error means that you need to implement this function
    to use this functionality

    e.g. you have to implement Simulation agent for interface
    when you create new one and you can not use existing
    """
    pass


def walkPhysInterfaces(intf: InterfaceBase):
    if intf._interfaces:
        for si in intf._interfaces:
            yield from walkPhysInterfaces(si)
    else:
        yield intf


def connectPacked(srcPacked: RtlSignalBase, dstInterface, exclude=None):
    """
    Connect 1D vector signal to this structuralized interface
    (LSB of first interface is LSB of result)

    :param packedSrc: vector which should be connected
    :param dstInterface: structuralized interface where should
        packedSrc be connected to
    :param exclude: sub interfaces of self which should be excluded
    """
    offset = 0
    connections = []
    for i in list(walkPhysInterfaces(dstInterface)):
        if exclude is not None and i in exclude:
            continue
        sig = i._sig
        t = sig._dtype
        w = t.bit_length()
        if w == 1:
            if srcPacked._dtype.bit_length() == 1:
                assert offset == 0, srcPacked
                s = srcPacked
            else:
                s = srcPacked[offset]
            offset += 1
        else:
            assert srcPacked._dtype.bit_length() >= w + offset, ("Insufficient amount of bits in srcPacked", srcPacked, w, offset)
            s = srcPacked[(w + offset): offset]  # src is likely to have insufficient amount of bits
            offset += w

        connections.append(sig(s))

    return connections


def walkFlatten(interface: InterfaceBase, shouldEnterIntfFn):
    """
    :param shouldEnterIntfFn: function (actual interface)
        returns tuple (shouldEnter, shouldYield)
    """
    _shouldEnter, _shouldYield = shouldEnterIntfFn(interface)
    if _shouldYield:
        yield interface

    if shouldEnterIntfFn:
        for intf in interface._interfaces:
            yield from walkFlatten(intf, shouldEnterIntfFn)


def packIntf(intf: InterfaceBase, masterDirEqTo=DIRECTION.OUT, exclude=None) -> Union[BitsVal, RtlSignalBase[Bits]]:
    """
    Concatenate all signals to one big signal, recursively
    (LSB of first interface is LSB of result)

    :param masterDirEqTo: only signals with this direction are packed
    :param exclude: sequence of signals/interfaces to exclude
    """
    if not intf._interfaces:
        if intf._masterDir == masterDirEqTo:
            return intf._sig
        return None

    res = None
    for i in intf._interfaces:
        if exclude is not None and i in exclude:
            continue

        if i._interfaces:
            if i._masterDir == DIRECTION.IN:
                d = DIRECTION.opposite(masterDirEqTo)
            else:
                d = masterDirEqTo
            s = packIntf(i, masterDirEqTo=d, exclude=exclude)
        else:
            if i._masterDir == masterDirEqTo:
                s = i._sig
            else:
                s = None

        if s is not None:
            if res is None:
                res = s._reinterpret_cast(Bits(s._dtype.bit_length()))
            else:
                res = s._concat(res)

    return res

1	from typing import Union	1✔
2
3	from hwt.hdl.constants import DIRECTION	1✔
4	from hwt.hdl.types.bits import Bits	1✔
5	from hwt.hdl.types.bitsVal import BitsVal	1✔
6	from hwt.synthesizer.interfaceLevel.mainBases import InterfaceBase	1✔
7	from hwt.synthesizer.rtlLevel.mainBases import RtlSignalBase	1✔
8
9
10	class NotSpecified(Exception):	1✔
11	"""
12	This error means that you need to implement this function
13	to use this functionality
14
15	e.g. you have to implement Simulation agent for interface
16	when you create new one and you can not use existing
17	"""
18	pass	1✔
19
20
21	def walkPhysInterfaces(intf: InterfaceBase):	1✔
22	if intf._interfaces:	1✔
23	for si in intf._interfaces:	1✔
24	yield from walkPhysInterfaces(si)	1✔
25	else:
26	yield intf	1✔
27
28
29	def connectPacked(srcPacked: RtlSignalBase, dstInterface, exclude=None):	1✔
30	"""
31	Connect 1D vector signal to this structuralized interface
32	(LSB of first interface is LSB of result)
33
34	:param packedSrc: vector which should be connected
35	:param dstInterface: structuralized interface where should
36	packedSrc be connected to
37	:param exclude: sub interfaces of self which should be excluded
38	"""
39	offset = 0	1✔
40	connections = []	1✔
41	for i in list(walkPhysInterfaces(dstInterface)):	1✔
42	if exclude is not None and i in exclude:	1✔
43	continue	1✔
44	sig = i._sig	1✔
45	t = sig._dtype	1✔
46	w = t.bit_length()	1✔
47	if w == 1:	1✔
48	if srcPacked._dtype.bit_length() == 1:	1✔
49	assert offset == 0, srcPacked	1✔
50	s = srcPacked	1✔
51	else:
52	s = srcPacked[offset]	1✔
53	offset += 1	1✔
54	else:
55	assert srcPacked._dtype.bit_length() >= w + offset, ("Insufficient amount of bits in srcPacked", srcPacked, w, offset)	1✔
56	s = srcPacked[(w + offset): offset] # src is likely to have insufficient amount of bits	1✔
57	offset += w	1✔
58
59	connections.append(sig(s))	1✔
60
61	return connections	1✔
62
63
64	def walkFlatten(interface: InterfaceBase, shouldEnterIntfFn):	1✔
65	"""
66	:param shouldEnterIntfFn: function (actual interface)
67	returns tuple (shouldEnter, shouldYield)
68	"""
UNCOV 69	_shouldEnter, _shouldYield = shouldEnterIntfFn(interface)	×
70	if _shouldYield:	×
71	yield interface	×
72
UNCOV 73	if shouldEnterIntfFn:	×
UNCOV 74	for intf in interface._interfaces:	×
UNCOV 75	yield from walkFlatten(intf, shouldEnterIntfFn)	×
76
77
78	def packIntf(intf: InterfaceBase, masterDirEqTo=DIRECTION.OUT, exclude=None) -> Union[BitsVal, RtlSignalBase[Bits]]:	1✔
79	"""
80	Concatenate all signals to one big signal, recursively
81	(LSB of first interface is LSB of result)
82
83	:param masterDirEqTo: only signals with this direction are packed
84	:param exclude: sequence of signals/interfaces to exclude
85	"""
86	if not intf._interfaces:	1!
UNCOV 87	if intf._masterDir == masterDirEqTo:	×
UNCOV 88	return intf._sig	×
UNCOV 89	return None	×
90
91	res = None	1✔
92	for i in intf._interfaces:	1✔
93	if exclude is not None and i in exclude:	1✔
94	continue	1✔
95
96	if i._interfaces:	1✔
97	if i._masterDir == DIRECTION.IN:	1!
UNCOV 98	d = DIRECTION.opposite(masterDirEqTo)	×
99	else:
100	d = masterDirEqTo	1✔
101	s = packIntf(i, masterDirEqTo=d, exclude=exclude)	1✔
102	else:
103	if i._masterDir == masterDirEqTo:	1!
104	s = i._sig	1✔
105	else:
UNCOV 106	s = None	×
107
108	if s is not None:	1!
109	if res is None:	1✔
110	res = s._reinterpret_cast(Bits(s._dtype.bit_length()))	1✔
111	else:
112	res = s._concat(res)	1✔
113
114	return res	1✔

Nic30 / hwt / 2be76794-4dd2-4abd-8081-a937932017ea

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