08ce248f-57b9-4179-82ce-9152efe813d7

Committed 09 Dec 2023 02:10PM UTC coverage: 88.002% (-0.02%) from 88.017%

Build # 08ce248f-57b9-4179-82ce-9152efe813d7

Build Type

push

circleci

Committed by

Nic30

Commit Message

fix: SimTestCase.randomize use clock freq. of associated clock

Run Details

3843 of 4700 branches covered (0.0%)

Branch coverage included in aggregate %.

6 of 8 new or added lines in 1 file covered. (75.0%)

9 existing lines in 1 file now uncovered.

11010 of 12178 relevant lines covered (90.41%)

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Source File
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79.76

/hwt/interfaces/utils.py

from typing import Union

from hwt.interfaces.std import Clk, Rst_n, Rst
from hwt.synthesizer.interfaceLevel.mainBases import UnitBase, InterfaceBase
from hwt.synthesizer.rtlLevel.constants import NOT_SPECIFIED


def addClkRstn(obj):
    """
    Construct clk, rst_n signal on object (usually Unit/Interface instance)
    * propagate CLK_FREQ to clk.FREQ
    """
    obj.clk = Clk()
    freq = getattr(obj, "CLK_FREQ", NOT_SPECIFIED)
    if freq is NOT_SPECIFIED:
        freq = getattr(obj, "FREQ", NOT_SPECIFIED)
    if freq is not NOT_SPECIFIED:
        obj.clk.FREQ = freq
    obj.rst_n = Rst_n()


def addClkRst(obj):
    """
    Construct clk, rst signal on object (usually Unit/Interface instance)
    * propagate CLK_FREQ to clk.FREQ
    """
    obj.clk = Clk()
    freq = getattr(obj, "CLK_FREQ", NOT_SPECIFIED)
    if freq is NOT_SPECIFIED:
        freq = getattr(obj, "FREQ", NOT_SPECIFIED)
    if freq is not NOT_SPECIFIED:
        obj.clk.FREQ = freq
    obj.rst = Rst()


def _tryConnect(src: InterfaceBase, unit: UnitBase, intfName: str):
    """
    Try connect src to interface of specified name on unit.
    Ignore if interface is not present or if it already has driver.
    """
    try:
        dst = getattr(unit, intfName)
    except AttributeError:
        return
    if not dst._sig.drivers:
        dst(src)
    return dst


def propagateClk(obj: Union[UnitBase, InterfaceBase]):
    """
    Propagate "clk" clock signal to all subcomponents
    """
    clk = obj.clk
    for u in obj._units:
        dstClk = _tryConnect(clk, u, 'clk')
        if dstClk is not None:
            assert dstClk.FREQ == clk.FREQ, (clk, "->", dstClk, clk.FREQ, dstClk.FREQ)


def propagateClkRstn(obj: Union[UnitBase, InterfaceBase]):
    """
    Propagate "clk" clock and negative reset "rst_n" signal
    to all subcomponents
    """
    clk = obj.clk
    rst_n = obj.rst_n

    for u in obj._units:
        _tryConnect(clk, u, 'clk')
        _tryConnect(rst_n, u, 'rst_n')
        _tryConnect(~rst_n, u, 'rst')


def propagateClkRst(obj: Union[UnitBase, InterfaceBase]):
    """
    Propagate "clk" clock and reset "rst" signal to all subcomponents
    """
    clk = obj.clk
    rst = obj.rst

    for u in obj._units:
        dstClk = _tryConnect(clk, u, 'clk')
        if dstClk is not None:
            assert dstClk.FREQ == clk.FREQ, (clk, "->", dstClk, clk.FREQ, dstClk.FREQ)

        _tryConnect(~rst, u, 'rst_n')
        _tryConnect(rst, u, 'rst')


def propagateRstn(obj):
    """
    Propagate negative reset "rst_n" signal
    to all subcomponents
    """
    rst_n = obj.rst_n

    for u in obj._units:
        _tryConnect(rst_n, u, 'rst_n')
        _tryConnect(~rst_n, u, 'rst')


def propagateRst(obj):
    """
    Propagate reset "rst" signal
    to all subcomponents
    """
    rst = obj.rst

    for u in obj._units:
        _tryConnect(~rst, u, 'rst_n')
        _tryConnect(rst, u, 'rst')

1	from typing import Union	1✔
2
3	from hwt.interfaces.std import Clk, Rst_n, Rst	1✔
4	from hwt.synthesizer.interfaceLevel.mainBases import UnitBase, InterfaceBase	1✔
5	from hwt.synthesizer.rtlLevel.constants import NOT_SPECIFIED	1✔
6
7
8	def addClkRstn(obj):	1✔
9	"""
10	Construct clk, rst_n signal on object (usually Unit/Interface instance)
11	* propagate CLK_FREQ to clk.FREQ
12	"""
13	obj.clk = Clk()	1✔
14	freq = getattr(obj, "CLK_FREQ", NOT_SPECIFIED)	1✔
15	if freq is NOT_SPECIFIED:	1✔
16	freq = getattr(obj, "FREQ", NOT_SPECIFIED)	1✔
17	if freq is not NOT_SPECIFIED:	1✔
18	obj.clk.FREQ = freq	1✔
19	obj.rst_n = Rst_n()	1✔
20
21
22	def addClkRst(obj):	1✔
23	"""
24	Construct clk, rst signal on object (usually Unit/Interface instance)
25	* propagate CLK_FREQ to clk.FREQ
26	"""
27	obj.clk = Clk()	1✔
28	freq = getattr(obj, "CLK_FREQ", NOT_SPECIFIED)	1✔
29	if freq is NOT_SPECIFIED:	1!
30	freq = getattr(obj, "FREQ", NOT_SPECIFIED)	1✔
31	if freq is not NOT_SPECIFIED:	1!
UNCOV 32	obj.clk.FREQ = freq	×
33	obj.rst = Rst()	1✔
34
35
36	def _tryConnect(src: InterfaceBase, unit: UnitBase, intfName: str):	1✔
37	"""
38	Try connect src to interface of specified name on unit.
39	Ignore if interface is not present or if it already has driver.
40	"""
41	try:	1✔
42	dst = getattr(unit, intfName)	1✔
43	except AttributeError:	1✔
44	return	1✔
45	if not dst._sig.drivers:	1✔
46	dst(src)	1✔
47	return dst	1✔
48
49
50	def propagateClk(obj: Union[UnitBase, InterfaceBase]):	1✔
51	"""
52	Propagate "clk" clock signal to all subcomponents
53	"""
54	clk = obj.clk	1✔
55	for u in obj._units:	1✔
56	dstClk = _tryConnect(clk, u, 'clk')	1✔
57	if dstClk is not None:	1!
58	assert dstClk.FREQ == clk.FREQ, (clk, "->", dstClk, clk.FREQ, dstClk.FREQ)	1✔
59
60
61	def propagateClkRstn(obj: Union[UnitBase, InterfaceBase]):	1✔
62	"""
63	Propagate "clk" clock and negative reset "rst_n" signal
64	to all subcomponents
65	"""
66	clk = obj.clk	1✔
67	rst_n = obj.rst_n	1✔
68
69	for u in obj._units:	1✔
70	_tryConnect(clk, u, 'clk')	1✔
71	_tryConnect(rst_n, u, 'rst_n')	1✔
72	_tryConnect(~rst_n, u, 'rst')	1✔
73
74
75	def propagateClkRst(obj: Union[UnitBase, InterfaceBase]):	1✔
76	"""
77	Propagate "clk" clock and reset "rst" signal to all subcomponents
78	"""
79	clk = obj.clk	1✔
80	rst = obj.rst	1✔
81
82	for u in obj._units:	1✔
83	dstClk = _tryConnect(clk, u, 'clk')	1✔
84	if dstClk is not None:	1!
85	assert dstClk.FREQ == clk.FREQ, (clk, "->", dstClk, clk.FREQ, dstClk.FREQ)	1✔
86
87	_tryConnect(~rst, u, 'rst_n')	1✔
88	_tryConnect(rst, u, 'rst')	1✔
89
90
91	def propagateRstn(obj):	1✔
92	"""
93	Propagate negative reset "rst_n" signal
94	to all subcomponents
95	"""
UNCOV 96	rst_n = obj.rst_n	×
97
UNCOV 98	for u in obj._units:	×
UNCOV 99	_tryConnect(rst_n, u, 'rst_n')	×
UNCOV 100	_tryConnect(~rst_n, u, 'rst')	×
101
102
103	def propagateRst(obj):	1✔
104	"""
105	Propagate reset "rst" signal
106	to all subcomponents
107	"""
UNCOV 108	rst = obj.rst	×
109
UNCOV 110	for u in obj._units:	×
UNCOV 111	_tryConnect(~rst, u, 'rst_n')	×
UNCOV 112	_tryConnect(rst, u, 'rst')	×

Nic30 / hwt / 08ce248f-57b9-4179-82ce-9152efe813d7

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