6979153563

Committed 24 Nov 2023 09:41AM UTC coverage: 63.032% (-0.1%) from 63.152%

Build # 6979153563

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Pull #1345

github

Committed by

rowleya

Commit Message

More type fixes and cast issues

Pull Request Pull Request #1345: Interdimensional compatibility

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29.5

/spynnaker/pyNN/external_devices_models/spif_retina_device.py

# Copyright (c) 2021 The University of Manchester
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
from spinn_utilities.overrides import overrides
from pacman.model.graphs.application import (
    Application2DFPGAVertex, FPGAConnection)
from pacman.model.routing_info import BaseKeyAndMask
from pacman.utilities.constants import BITS_IN_KEY
from pacman.utilities.utility_calls import is_power_of_2
from spinn_front_end_common.abstract_models import (
    AbstractSendMeMulticastCommandsVertex)
from spinn_front_end_common.utilities.exceptions import ConfigurationException
from spynnaker.pyNN.models.common import PopulationApplicationVertex
from .spif_devices import (
    SPIF_FPGA_ID, SPIF_OUTPUT_FPGA_LINK, SPIF_INPUT_FPGA_LINKS,
    N_PIPES, N_FILTERS, SpiNNFPGARegister, SPIFRegister,
    set_field_mask, set_field_shift, set_field_limit,
    set_filter_mask, set_filter_value, set_mapper_key,
    set_input_key, set_input_mask, set_input_route)


class SPIFRetinaDevice(
        Application2DFPGAVertex, PopulationApplicationVertex,
        AbstractSendMeMulticastCommandsVertex):
    """
    A retina device connected to SpiNNaker using a SPIF board.
    """

    #: SPIF outputs to 8 FPGA output links, so we split into (2 x 4), meaning
    #: a mask of (1 x 3)
    Y_MASK = 1

    #: See Y_MASK for description
    X_MASK = 3

    #: The number of X values per row
    X_PER_ROW = 4

    #: The number of devices in existence, to work out the key
    __n_devices = 0

    __slots__ = (
        "__spif_mask",
        "__index_by_slice",
        "__base_key",
        "__pipe",
        "__input_y_mask",
        "__input_y_shift",
        "__input_x_mask",
        "__input_x_shift")

    @classmethod
    def __issue_device_id(cls, base_key):
        if base_key is None:
            base_key = cls.__n_devices
        cls.__n_devices += 1
        return base_key

    def __init__(self, pipe, width, height, sub_width, sub_height,
                 base_key=None, input_x_shift=16, input_y_shift=0,
                 board_address=None, chip_coords=None):
        """
        :param int pipe: Which pipe on SPIF the retina is connected to
        :param int width: The width of the retina in pixels
        :param int height: The height of the retina in pixels
        :param int sub_width:
            The width of rectangles to split the retina into for efficiency of
            sending
        :param int sub_height:
            The height of rectangles to split the retina into for efficiency of
            sending
        :param base_key:
            The key that is common over the whole vertex,
            or `None` to use the pipe number as the key
        :type base_key: int or None
        :param int input_x_shift:
            The shift to get the x coordinate from the input keys sent to SPIF
        :param int input_y_shift:
            The shift to get the y coordinate from the input keys sent to SPIF
        :param board_address:
            The IP address of the board to which the FPGA is connected,
            or `None` to use the default board or chip_coords.

            .. note::
                chip_coords will be used first if both are specified, with
                board_address then being used if the coordinates don't connect
                to an FPGA.
        :type board_address: str or None
        :param chip_coords:
            The coordinates of the chip to which the FPGA is connected, or
            `None` to use the default board or board_address.

            .. note::
                chip_coords will be used first if board_address is also
                specified, with board_address then being used if the
                coordinates don't connect to an FPGA.
        :type chip_coords: tuple(int, int) or None
        """
        # Do some checks
        if sub_width < self.X_MASK + 1 or sub_height < self.Y_MASK + 1:
            raise ConfigurationException(
                "The sub-squares must be >=4 x >= 2"
                f" ({sub_width} x {sub_height} specified)")
        if pipe >= N_PIPES:
            raise ConfigurationException(
                f"Pipe {pipe} is bigger than maximum allowed {N_PIPES}")

        # The width has to be a power of 2 as otherwise the keys will not line
        # up correctly (x is at the LSB of the key, so key then has an x
        # field).  This is an error here as it affects the downstream
        # population calculations also!
        if not is_power_of_2(width):
            raise ConfigurationException(
                "The width of the SPIF retina must be a power of 2.  If the"
                " real retina size is less than this, please round it up."
                " This will ensure that following Populations can decode the"
                " spikes correctly.  Note that you will also have to make the"
                " sizes of the following Populations bigger to match!")

        # Call the super
        super().__init__(
            width, height, sub_width, sub_height,
            self.__incoming_fpgas(board_address, chip_coords),
            self.__outgoing_fpga(board_address, chip_coords))

        # The mask is going to be made up of:
        # | K | P | Y_I | Y_0 | Y_F | X_I | X_0 | X_F |
        # K = base key
        # P = polarity (0 as not cared about)
        # Y_I = y index of sub-square
        # Y_0 = 0s for values not cared about in Y
        # Y_F = FPGA y index
        # X_I = x index of sub-square
        # X_0 = 0s for values not cared about in X
        # X_F = FPGA x index
        # Now - go calculate:
        x_bits = self._x_bits
        y_bits = self._y_bits

        # Mask to apply to route packets at input
        n_key_bits = BITS_IN_KEY - self._key_shift
        key_mask = (1 << n_key_bits) - 1
        self.__spif_mask = (
            (key_mask << self._key_shift) +
            (self.Y_MASK << self._source_y_shift) +
            (self.X_MASK << self._source_x_shift))

        # A dictionary to get vertex index from FPGA and slice
        self.__index_by_slice = dict()

        self.__pipe = pipe
        self.__base_key = self.__issue_device_id(base_key)

        # Generate the shifts and masks to convert the SPIF Ethernet inputs to
        # PYX format
        self.__input_x_mask = ((1 << x_bits) - 1) << input_x_shift
        self.__input_x_shift = self.__unsigned(input_x_shift)
        self.__input_y_mask = ((1 << y_bits) - 1) << input_y_shift
        self.__input_y_shift = self.__unsigned(input_y_shift - x_bits)

    @staticmethod
    def __unsigned(n):
        return n & 0xFFFFFFFF

    def __incoming_fpgas(self, board_address, chip_coords):
        """
        Get the incoming FPGA connections.

        :rtype: list(FPGAConnection)
        """
        # We use every other odd link
        return [FPGAConnection(SPIF_FPGA_ID, i, board_address, chip_coords)
                for i in SPIF_INPUT_FPGA_LINKS]

    def __outgoing_fpga(self, board_address, chip_coords):
        """
        Get the outgoing FPGA connection (for commands).

        :rtype: FGPA_Connection
        """
        return FPGAConnection(
            SPIF_FPGA_ID, SPIF_OUTPUT_FPGA_LINK, board_address, chip_coords)

    def __fpga_indices(self, fpga_link_id):
        # We use every other odd link, so we can work out the "index" of the
        # link in the list as follows, and we can then split the index into
        # x and y components
        fpga_index = (fpga_link_id - 1) // 2
        fpga_x_index = fpga_index % self.X_PER_ROW
        fpga_y_index = fpga_index // self.X_PER_ROW
        return fpga_x_index, fpga_y_index

    @overrides(Application2DFPGAVertex.get_incoming_slice_for_link)
    def get_incoming_slice_for_link(self, link, index):
        vertex_slice = super().get_incoming_slice_for_link(link, index)
        self.__index_by_slice[link.fpga_link_id, vertex_slice] = index
        return vertex_slice

    @overrides(Application2DFPGAVertex.get_machine_fixed_key_and_mask)
    def get_machine_fixed_key_and_mask(self, machine_vertex, partition_id):
        fpga_link_id = machine_vertex.fpga_link_id
        vertex_slice = machine_vertex.vertex_slice
        index = self.__index_by_slice[fpga_link_id, vertex_slice]
        key_and_mask = self._get_key_and_mask(self.__base_key, index)

        fpga_x, fpga_y = self.__fpga_indices(fpga_link_id)

        # Build the key from the components
        fpga_key = key_and_mask.key + (
            (fpga_y << self._source_y_shift) +
            (fpga_x << self._source_x_shift))
        fpga_mask = key_and_mask.mask | self.__spif_mask
        return BaseKeyAndMask(fpga_key, fpga_mask)

    @overrides(Application2DFPGAVertex.get_fixed_key_and_mask)
    def get_fixed_key_and_mask(self, partition_id):
        n_key_bits = BITS_IN_KEY - self._key_shift
        key_mask = ((1 << n_key_bits) - 1) << self._key_shift
        return BaseKeyAndMask(self.__base_key << self._key_shift, key_mask)

    @property
    @overrides(AbstractSendMeMulticastCommandsVertex.start_resume_commands)
    def start_resume_commands(self):
        # Make sure everything has stopped
        commands = [SpiNNFPGARegister.STOP.cmd()]

        # Clear the counters
        commands.append(SPIFRegister.OUT_PERIPH_PKT_CNT.cmd(0))
        commands.append(SPIFRegister.CONFIG_PKT_CNT.cmd(0))
        commands.append(SPIFRegister.DROPPED_PKT_CNT.cmd(0))
        commands.append(SPIFRegister.IN_PERIPH_PKT_CNT.cmd(0))

        # Configure the creation of packets from fields to keys using the
        # "standard" input to SPIF (X | P | Y) and convert to (Y | X)
        commands.extend([
            set_field_mask(self.__pipe, 0, self.__input_x_mask),
            set_field_shift(self.__pipe, 0, self.__input_x_shift),
            set_field_limit(self.__pipe, 0,
                            (self.width - 1) << self._source_x_shift),
            set_field_mask(self.__pipe, 1, self.__input_y_mask),
            set_field_shift(self.__pipe, 1, self.__input_y_shift),
            set_field_limit(self.__pipe, 1,
                            (self.height - 1) << self._source_y_shift),
            # These are unused but set them to be sure
            set_field_mask(self.__pipe, 2, 0),
            set_field_shift(self.__pipe, 2, 0),
            set_field_limit(self.__pipe, 2, 0),
            set_field_mask(self.__pipe, 3, 0),
            set_field_shift(self.__pipe, 3, 0),
            set_field_limit(self.__pipe, 3, 0)
        ])

        # Don't filter
        commands.extend([
            set_filter_mask(self.__pipe, i, 0) for i in range(N_FILTERS)
        ])
        commands.extend([
            set_filter_value(self.__pipe, i, 1) for i in range(N_FILTERS)
        ])

        # Configure the output routing key
        commands.append(set_mapper_key(
            self.__pipe, self.__base_key << self._key_shift))

        # Configure the links to send packets to the 8 FPGAs using the
        # lower bits
        commands.extend(
            set_input_key(self.__pipe, i, self.__spif_key(15 - (i * 2)))
            for i in range(8))
        commands.extend(
            set_input_mask(self.__pipe, i, self.__spif_mask)
            for i in range(8))
        commands.extend(
            set_input_route(self.__pipe, i, i)
            for i in range(8))

        # Send the start signal
        commands.append(SpiNNFPGARegister.START.cmd())

        return commands

    def __spif_key(self, fpga_link_id):
        x, y = self.__fpga_indices(fpga_link_id)
        return ((self.__base_key << self._key_shift) +
                (x << self._source_x_shift) +
                (y << self._source_y_shift))

    @property
    @overrides(AbstractSendMeMulticastCommandsVertex.pause_stop_commands)
    def pause_stop_commands(self):
        # Send the stop signal
        yield SpiNNFPGARegister.STOP.cmd()

    @property
    @overrides(AbstractSendMeMulticastCommandsVertex.timed_commands)
    def timed_commands(self):
        return []

    @overrides(PopulationApplicationVertex.get_atom_key_map)
    def get_atom_key_map(self, pre_vertex, partition_id, routing_info):
        # Work out which machine vertex
        x_start, y_start = pre_vertex.vertex_slice.start
        key_and_mask = self.get_machine_fixed_key_and_mask(
            pre_vertex, partition_id)
        x_end = x_start + self.sub_width
        y_end = y_start + self.sub_height
        key_x = (key_and_mask.key >> self._source_x_shift) & self.X_MASK
        key_y = (key_and_mask.key >> self._source_y_shift) & self.Y_MASK
        neuron_id = (pre_vertex.vertex_slice.lo_atom +
                     (key_y * self.X_PER_ROW) + key_x)
        for x in range(x_start, x_end, self.X_MASK + 1):
            for y in range(y_start, y_end, self.Y_MASK + 1):
                key = (key_and_mask.key | (x << self._source_x_shift) |
                       (y << self._source_y_shift))
                yield (neuron_id, key)
                neuron_id += self.X_PER_ROW

1	# Copyright (c) 2021 The University of Manchester
2	#
3	# Licensed under the Apache License, Version 2.0 (the "License");
4	# you may not use this file except in compliance with the License.
5	# You may obtain a copy of the License at
6	#
7	# https://www.apache.org/licenses/LICENSE-2.0
8	#
9	# Unless required by applicable law or agreed to in writing, software
10	# distributed under the License is distributed on an "AS IS" BASIS,
11	# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12	# See the License for the specific language governing permissions and
13	# limitations under the License.
14	from spinn_utilities.overrides import overrides	1✔
15	from pacman.model.graphs.application import (	1✔
16	Application2DFPGAVertex, FPGAConnection)
17	from pacman.model.routing_info import BaseKeyAndMask	1✔
18	from pacman.utilities.constants import BITS_IN_KEY	1✔
19	from pacman.utilities.utility_calls import is_power_of_2	1✔
20	from spinn_front_end_common.abstract_models import (	1✔
21	AbstractSendMeMulticastCommandsVertex)
22	from spinn_front_end_common.utilities.exceptions import ConfigurationException	1✔
23	from spynnaker.pyNN.models.common import PopulationApplicationVertex	1✔
24	from .spif_devices import (	1✔
25	SPIF_FPGA_ID, SPIF_OUTPUT_FPGA_LINK, SPIF_INPUT_FPGA_LINKS,
26	N_PIPES, N_FILTERS, SpiNNFPGARegister, SPIFRegister,
27	set_field_mask, set_field_shift, set_field_limit,
28	set_filter_mask, set_filter_value, set_mapper_key,
29	set_input_key, set_input_mask, set_input_route)
30
31
32	class SPIFRetinaDevice(	1✔
33	Application2DFPGAVertex, PopulationApplicationVertex,
34	AbstractSendMeMulticastCommandsVertex):
35	"""
36	A retina device connected to SpiNNaker using a SPIF board.
37	"""
38
39	#: SPIF outputs to 8 FPGA output links, so we split into (2 x 4), meaning
40	#: a mask of (1 x 3)
41	Y_MASK = 1	1✔
42
43	#: See Y_MASK for description
44	X_MASK = 3	1✔
45
46	#: The number of X values per row
47	X_PER_ROW = 4	1✔
48
49	#: The number of devices in existence, to work out the key
50	__n_devices = 0	1✔
51
52	__slots__ = (	1✔
53	"__spif_mask",
54	"__index_by_slice",
55	"__base_key",
56	"__pipe",
57	"__input_y_mask",
58	"__input_y_shift",
59	"__input_x_mask",
60	"__input_x_shift")
61
62	@classmethod	1✔
63	def __issue_device_id(cls, base_key):	1✔
64	if base_key is None:	×
65	base_key = cls.__n_devices	×
66	cls.__n_devices += 1	×
67	return base_key	×
68
69	def __init__(self, pipe, width, height, sub_width, sub_height,	1✔
70	base_key=None, input_x_shift=16, input_y_shift=0,
71	board_address=None, chip_coords=None):
72	"""
73	:param int pipe: Which pipe on SPIF the retina is connected to
74	:param int width: The width of the retina in pixels
75	:param int height: The height of the retina in pixels
76	:param int sub_width:
77	The width of rectangles to split the retina into for efficiency of
78	sending
79	:param int sub_height:
80	The height of rectangles to split the retina into for efficiency of
81	sending
82	:param base_key:
83	The key that is common over the whole vertex,
84	or `None` to use the pipe number as the key
85	:type base_key: int or None
86	:param int input_x_shift:
87	The shift to get the x coordinate from the input keys sent to SPIF
88	:param int input_y_shift:
89	The shift to get the y coordinate from the input keys sent to SPIF
90	:param board_address:
91	The IP address of the board to which the FPGA is connected,
92	or `None` to use the default board or chip_coords.
93
94	.. note::
95	chip_coords will be used first if both are specified, with
96	board_address then being used if the coordinates don't connect
97	to an FPGA.
98	:type board_address: str or None
99	:param chip_coords:
100	The coordinates of the chip to which the FPGA is connected, or
101	`None` to use the default board or board_address.
102
103	.. note::
104	chip_coords will be used first if board_address is also
105	specified, with board_address then being used if the
106	coordinates don't connect to an FPGA.
107	:type chip_coords: tuple(int, int) or None
108	"""
109	# Do some checks
NEW 110	if sub_width < self.X_MASK + 1 or sub_height < self.Y_MASK + 1:	×
111	raise ConfigurationException(	×
112	"The sub-squares must be >=4 x >= 2"
113	f" ({sub_width} x {sub_height} specified)")
114	if pipe >= N_PIPES:	×
115	raise ConfigurationException(	×
116	f"Pipe {pipe} is bigger than maximum allowed {N_PIPES}")
117
118	# The width has to be a power of 2 as otherwise the keys will not line
119	# up correctly (x is at the LSB of the key, so key then has an x
120	# field). This is an error here as it affects the downstream
121	# population calculations also!
NEW 122	if not is_power_of_2(width):	×
NEW 123	raise ConfigurationException(	×
124	"The width of the SPIF retina must be a power of 2. If the"
125	" real retina size is less than this, please round it up."
126	" This will ensure that following Populations can decode the"
127	" spikes correctly. Note that you will also have to make the"
128	" sizes of the following Populations bigger to match!")
129
130	# Call the super
131	super().__init__(	×
132	width, height, sub_width, sub_height,
133	self.__incoming_fpgas(board_address, chip_coords),
134	self.__outgoing_fpga(board_address, chip_coords))
135
136	# The mask is going to be made up of:
137	# \| K \| P \| Y_I \| Y_0 \| Y_F \| X_I \| X_0 \| X_F \|
138	# K = base key
139	# P = polarity (0 as not cared about)
140	# Y_I = y index of sub-square
141	# Y_0 = 0s for values not cared about in Y
142	# Y_F = FPGA y index
143	# X_I = x index of sub-square
144	# X_0 = 0s for values not cared about in X
145	# X_F = FPGA x index
146	# Now - go calculate:
147	x_bits = self._x_bits	×
148	y_bits = self._y_bits	×
149
150	# Mask to apply to route packets at input
151	n_key_bits = BITS_IN_KEY - self._key_shift	×
152	key_mask = (1 << n_key_bits) - 1	×
153	self.__spif_mask = (	×
154	(key_mask << self._key_shift) +
155	(self.Y_MASK << self._source_y_shift) +
156	(self.X_MASK << self._source_x_shift))
157
158	# A dictionary to get vertex index from FPGA and slice
159	self.__index_by_slice = dict()	×
160
161	self.__pipe = pipe	×
162	self.__base_key = self.__issue_device_id(base_key)	×
163
164	# Generate the shifts and masks to convert the SPIF Ethernet inputs to
165	# PYX format
166	self.__input_x_mask = ((1 << x_bits) - 1) << input_x_shift	×
167	self.__input_x_shift = self.__unsigned(input_x_shift)	×
168	self.__input_y_mask = ((1 << y_bits) - 1) << input_y_shift	×
169	self.__input_y_shift = self.__unsigned(input_y_shift - x_bits)	×
170
171	@staticmethod	1✔
172	def __unsigned(n):	1✔
173	return n & 0xFFFFFFFF	×
174
175	def __incoming_fpgas(self, board_address, chip_coords):	1✔
176	"""
177	Get the incoming FPGA connections.
178
179	:rtype: list(FPGAConnection)
180	"""
181	# We use every other odd link
182	return [FPGAConnection(SPIF_FPGA_ID, i, board_address, chip_coords)	×
183	for i in SPIF_INPUT_FPGA_LINKS]
184
185	def __outgoing_fpga(self, board_address, chip_coords):	1✔
186	"""
187	Get the outgoing FPGA connection (for commands).
188
189	:rtype: FGPA_Connection
190	"""
191	return FPGAConnection(	×
192	SPIF_FPGA_ID, SPIF_OUTPUT_FPGA_LINK, board_address, chip_coords)
193
194	def __fpga_indices(self, fpga_link_id):	1✔
195	# We use every other odd link, so we can work out the "index" of the
196	# link in the list as follows, and we can then split the index into
197	# x and y components
198	fpga_index = (fpga_link_id - 1) // 2	×
199	fpga_x_index = fpga_index % self.X_PER_ROW	×
200	fpga_y_index = fpga_index // self.X_PER_ROW	×
201	return fpga_x_index, fpga_y_index	×
202
203	@overrides(Application2DFPGAVertex.get_incoming_slice_for_link)	1✔
204	def get_incoming_slice_for_link(self, link, index):	1✔
205	vertex_slice = super().get_incoming_slice_for_link(link, index)	×
206	self.__index_by_slice[link.fpga_link_id, vertex_slice] = index	×
207	return vertex_slice	×
208
209	@overrides(Application2DFPGAVertex.get_machine_fixed_key_and_mask)	1✔
210	def get_machine_fixed_key_and_mask(self, machine_vertex, partition_id):	1✔
211	fpga_link_id = machine_vertex.fpga_link_id	×
212	vertex_slice = machine_vertex.vertex_slice	×
213	index = self.__index_by_slice[fpga_link_id, vertex_slice]	×
214	key_and_mask = self._get_key_and_mask(self.__base_key, index)	×
215
216	fpga_x, fpga_y = self.__fpga_indices(fpga_link_id)	×
217
218	# Build the key from the components
219	fpga_key = key_and_mask.key + (	×
220	(fpga_y << self._source_y_shift) +
221	(fpga_x << self._source_x_shift))
222	fpga_mask = key_and_mask.mask \| self.__spif_mask	×
223	return BaseKeyAndMask(fpga_key, fpga_mask)	×
224
225	@overrides(Application2DFPGAVertex.get_fixed_key_and_mask)	1✔
226	def get_fixed_key_and_mask(self, partition_id):	1✔
227	n_key_bits = BITS_IN_KEY - self._key_shift	×
228	key_mask = ((1 << n_key_bits) - 1) << self._key_shift	×
229	return BaseKeyAndMask(self.__base_key << self._key_shift, key_mask)	×
230
231	@property	1✔
232	@overrides(AbstractSendMeMulticastCommandsVertex.start_resume_commands)	1✔
233	def start_resume_commands(self):	1✔
234	# Make sure everything has stopped
NEW 235	commands = [SpiNNFPGARegister.STOP.cmd()]	×
236
237	# Clear the counters
NEW 238	commands.append(SPIFRegister.OUT_PERIPH_PKT_CNT.cmd(0))	×
NEW 239	commands.append(SPIFRegister.CONFIG_PKT_CNT.cmd(0))	×
NEW 240	commands.append(SPIFRegister.DROPPED_PKT_CNT.cmd(0))	×
NEW 241	commands.append(SPIFRegister.IN_PERIPH_PKT_CNT.cmd(0))	×
242
243	# Configure the creation of packets from fields to keys using the
244	# "standard" input to SPIF (X \| P \| Y) and convert to (Y \| X)
NEW 245	commands.extend([	×
246	set_field_mask(self.__pipe, 0, self.__input_x_mask),
247	set_field_shift(self.__pipe, 0, self.__input_x_shift),
248	set_field_limit(self.__pipe, 0,
249	(self.width - 1) << self._source_x_shift),
250	set_field_mask(self.__pipe, 1, self.__input_y_mask),
251	set_field_shift(self.__pipe, 1, self.__input_y_shift),
252	set_field_limit(self.__pipe, 1,
253	(self.height - 1) << self._source_y_shift),
254	# These are unused but set them to be sure
255	set_field_mask(self.__pipe, 2, 0),
256	set_field_shift(self.__pipe, 2, 0),
257	set_field_limit(self.__pipe, 2, 0),
258	set_field_mask(self.__pipe, 3, 0),
259	set_field_shift(self.__pipe, 3, 0),
260	set_field_limit(self.__pipe, 3, 0)
261	])
262
263	# Don't filter
NEW 264	commands.extend([	×
265	set_filter_mask(self.__pipe, i, 0) for i in range(N_FILTERS)
266	])
NEW 267	commands.extend([	×
268	set_filter_value(self.__pipe, i, 1) for i in range(N_FILTERS)
269	])
270
271	# Configure the output routing key
NEW 272	commands.append(set_mapper_key(	×
273	self.__pipe, self.__base_key << self._key_shift))
274
275	# Configure the links to send packets to the 8 FPGAs using the
276	# lower bits
NEW 277	commands.extend(	×
278	set_input_key(self.__pipe, i, self.__spif_key(15 - (i * 2)))
279	for i in range(8))
NEW 280	commands.extend(	×
281	set_input_mask(self.__pipe, i, self.__spif_mask)
282	for i in range(8))
NEW 283	commands.extend(	×
284	set_input_route(self.__pipe, i, i)
285	for i in range(8))
286
287	# Send the start signal
NEW 288	commands.append(SpiNNFPGARegister.START.cmd())	×
289
NEW 290	return commands	×
291
292	def __spif_key(self, fpga_link_id):	1✔
293	x, y = self.__fpga_indices(fpga_link_id)	×
294	return ((self.__base_key << self._key_shift) +	×
295	(x << self._source_x_shift) +
296	(y << self._source_y_shift))
297
298	@property	1✔
299	@overrides(AbstractSendMeMulticastCommandsVertex.pause_stop_commands)	1✔
300	def pause_stop_commands(self):	1✔
301	# Send the stop signal
302	yield SpiNNFPGARegister.STOP.cmd()	×
303
304	@property	1✔
305	@overrides(AbstractSendMeMulticastCommandsVertex.timed_commands)	1✔
306	def timed_commands(self):	1✔
307	return []	×
308
309	@overrides(PopulationApplicationVertex.get_atom_key_map)	1✔
310	def get_atom_key_map(self, pre_vertex, partition_id, routing_info):	1✔
311	# Work out which machine vertex
312	x_start, y_start = pre_vertex.vertex_slice.start	×
313	key_and_mask = self.get_machine_fixed_key_and_mask(	×
314	pre_vertex, partition_id)
NEW 315	x_end = x_start + self.sub_width	×
NEW 316	y_end = y_start + self.sub_height	×
317	key_x = (key_and_mask.key >> self._source_x_shift) & self.X_MASK	×
318	key_y = (key_and_mask.key >> self._source_y_shift) & self.Y_MASK	×
319	neuron_id = (pre_vertex.vertex_slice.lo_atom +	×
320	(key_y * self.X_PER_ROW) + key_x)
321	for x in range(x_start, x_end, self.X_MASK + 1):	×
322	for y in range(y_start, y_end, self.Y_MASK + 1):	×
323	key = (key_and_mask.key \| (x << self._source_x_shift) \|	×
324	(y << self._source_y_shift))
325	yield (neuron_id, key)	×
326	neuron_id += self.X_PER_ROW	×

SpiNNakerManchester / sPyNNaker / 6979153563

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