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Merge pull request #1408 from SpiNNakerManchester/spif_multi_output

Spif Multi Output

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/spynnaker/pyNN/external_devices_models/spif_devices.py

# Copyright (c) 2022 The University of Manchester
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""
Devices connected to the SpiNNaker peripheral interface (`SPIF`_).

.. _SPIF: https://github.com/SpiNNakerManchester/spif

"""

from enum import IntEnum
from spinn_front_end_common.utility_models import MultiCastCommand
from spinn_utilities.overrides import overrides

_REPEATS = 2
_DELAY_BETWEEN_REPEATS = 1

#: Base key to send packets to SpiNNaker FPGA (add register offset)
_LC_KEY = 0xFFFFFE00

#: Base key to send packets to SPIF (add register offset)
_RC_KEY = 0xFFFFFF00

#: The number of pipes
N_PIPES = 2

#: The number of fields supported for each pipe
N_FIELDS = 4

#: The number of filters supported for each pipe
N_FILTERS = 8

#: The number of FPGA inputs per pipe
#:
#: .. note::
#:     The 16 inputs are not actually separated in the hardware,
#:     but a logical separation per pipe is useful.
N_INPUTS = 8

#: SPIF is always connected to FPGA 0
SPIF_FPGA_ID = 0

#: SPIF always outputs to FPGA link 15 on FPGA 0
SPIF_OUTPUT_FPGA_LINK = 15

#: SPIF always gets input from odd links on FPGA 0 (1, 3, 5, 7, 9, 11, 13, 15)
SPIF_INPUT_FPGA_LINKS = range(1, 16, 2)


class SPIFRegister(IntEnum):
    """
    The register offsets on a SPIF device.
    """
    #: The key to send messages back when requested
    REPLY_KEY = 2

    #: The input key register base (8 inputs per pipe)
    IR_KEY_BASE = 16

    #: The input mask register base (8 inputs per pipe)
    IR_MASK_BASE = 32

    #: The input route register base (8 inputs per pipe)
    IR_ROUTE_BASE = 48

    #: The output peripheral packet count register
    OUT_PERIPH_PKT_CNT = 64

    #: The configuration packet count register
    CONFIG_PKT_CNT = 65

    #: The dropped packet count register
    DROPPED_PKT_CNT = 66

    #: The input peripheral packet count register
    IN_PERIPH_PKT_CNT = 67

    #: The output mapper key base register (2 pipes)
    MP_KEY_BASE = 80

    #: The output mapper field mask base register (4 fields per pipe)
    MP_FLD_MASK_BASE = 96

    #: The output mapper field shift base register (4 fields per pipe)
    MP_FLD_SHIFT_BASE = 112

    #: The output mapper field limit base register (4 fields per pipe)
    MP_FLD_LIMIT_BASE = 128

    #: The filter value base register (8 filters per pipe)
    FL_VALUE_BASE = 144

    #: The filter mask base register (8 filters per pipe)
    FL_MASK_BASE = 176

    # The distiller key base register (6 distillers)
    DIST_KEY_BASE = 208

    # The distiller key mask register (6 distillers)
    DIST_MASK_BASE = 224

    # The distiller key shift register (6 distillers)
    DIST_SHIFT_BASE = 240

    def cmd(self, payload=None, index=0):
        """
        Make a command to send to a SPIF device to set a register value.

        :param payload:
            The payload to use in the command, or `None` for no payload
        :type payload: int or None
        :param int index:
            The index of the register to send to when there are multiple
            registers starting from a base
        :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
        """
        return MultiCastCommand(
            _RC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
            delay_between_repeats=_DELAY_BETWEEN_REPEATS)

    def delayed_command(self, get_payload, index=0):
        """ Make a command to send to a SPIF device to set a register value,
            where the value itself is currently unknown

        :param func()->int get_payload:
            A function to call to get the payload later
        :param int index:
            The index of the register to use when using a multi-indexed
            register (default is 0 which works for all registers)
        :rtype: MultiCastCommand
        """
        return _DelayedMultiCastCommand(
            _RC_KEY + self.value + index, get_payload, repeat=_REPEATS,
            delay_between_repeats=_DELAY_BETWEEN_REPEATS, index=index)


def set_mapper_key(pipe, key):
    """
    Get a command to set the output base key for packets from SPIF.  This
    will be added to the keys determined by the mapper output.

    :param int pipe: The SPIF pipe to set the key of (0-1)
    :param int key: The output key to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_KEY_BASE.cmd(key, pipe)


def set_field_mask(pipe, index, mask):
    """
    Get a command to set the mask of a mapper field on SPIF.  This masks
    off the bits of the field from the incoming UDP or USB packet values
    (which are 32-bits each).

    :param int pipe: The SPIF pipe to set the mask of (0-1)
    :param int index: The index of the field to set (0-3)
    :param int mask: The mask to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_FLD_MASK_BASE.cmd(mask, (pipe * N_FIELDS) + index)


def set_field_shift(pipe, index, shift):
    """
    Get a command to set the shift of a mapper field on SPIF.  This shifts
    the masked bits of the field from the incoming UDP or USB packet values
    (which are 32-bits each).

    :param int pipe: The SPIF pipe to set the shift of (0-1)
    :param int index: The index of the field to set (0-3)
    :param int shift:
        The shift value to set (0-31); positive = right, negative = left
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_FLD_SHIFT_BASE.cmd(
        shift, (pipe * N_FIELDS) + index)


def set_field_limit(pipe, index, limit):
    """
    Get a command to set the limit of a mapper field on SPIF.  This sets
    a limit on the value of the field after shifting and masking.

    :param int pipe: The SPIF pipe to set the limit of (0-1)
    :param int index: The index of the field to set (0-3)
    :param int limit: The maximum value of the field
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_FLD_LIMIT_BASE.cmd(
        limit, (pipe * N_FIELDS) + index)


def set_filter_value(pipe, index, value):
    """
    Get a command to set the value of a filter of SPIF.  This will drop
    input events from the UDP or USB packets where filter value ==
    filter mask & event value.

    :param int pipe: The SPIF pipe to set the filter of (0-1)
    :param int index: The index of the filter to set (0-7)
    :param int value: The filter value to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.FL_VALUE_BASE.cmd(
        value, (pipe * N_FILTERS) + index)


def set_filter_mask(pipe, index, mask):
    """
    Get a command to set the mask of a filter of SPIF.  This will drop
    input events from the UDP or USB packets where filter value ==
    filter mask & event value.

    :param int pipe: The SPIF pipe to set the filter of (0-1)
    :param int index: The index of the filter to set (0-7)
    :param int mask: The filter mask to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.FL_MASK_BASE.cmd(
        mask, (pipe * N_FILTERS) + index)


def set_input_key(pipe, index, key):
    """
    Get a command to set the key of the FPGA input of SPIF.  This tells
    SPIF how to route the incoming packets after they have been assembled
    by the mapper; when incoming key & input mask == input_key, the packet
    will be routed to input_route.

    :param int pipe: The SPIF pipe to set the input of (0-1)
    :param int index: The index of the input to set (0-7)
    :param int key: The key to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.IR_KEY_BASE.cmd(key, (pipe * N_INPUTS) + index)


def set_input_mask(pipe, index, mask):
    """
    Get a command to set the mask of the FPGA input of SPIF.  This tells
    SPIF how to route the incoming packets after they have been assembled
    by the mapper; when incoming key & input mask == input_key, the packet
    will be routed to input_route.

    :param int pipe: The SPIF pipe to set the input of (0-1)
    :param int index: The index of the input to set (0-7)
    :param int mask: The mask to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.IR_MASK_BASE.cmd(mask, (pipe * N_INPUTS) + index)


def set_input_route(pipe, index, route):
    """
    Get a command to set the route of the FPGA input of SPIF.  This tells
    SPIF how to route the incoming packets after they have been assembled
    by the mapper; when incoming key & input mask == input_key, the packet
    will be routed to input_route.

    .. note::
        route 0 refers to FPGA link 15, 1 to 13 and so on in twos.

    :param int pipe: The SPIF pipe to set the input of (0-1)
    :param int index: The index of the input to set (0-7)
    :param int route: The route to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.IR_ROUTE_BASE.cmd(route, (pipe * N_INPUTS) + index)


def set_distiller_key(index, key):
    """ Get a command to set the key of the distiller of the output via SPIF.
        This tells SPIF which bits to put at the top of the 32-bit output for
        each spike received on the given distiller channel, defined by the
        peripheral routes in the SpiNNaker FPGA.

    :param int index: The index of the channel to set (0-5)
    :param int key: The key to set
    :rtype: MulticastCommand
    """
    return SPIFRegister.DIST_KEY_BASE.cmd(key, index)


def set_distiller_mask(index, mask):
    """ Get a command to set the mask of the distiller of the output via SPIF.
        This tells SPIF which bits to use from the key in the 32-bit output for
        each spike received on the given distiller channel, defined by the
        peripheral routes in the SpiNNaker FPGA.

    :param int index: The index of the channel to set (0-5)
    :param int mask: The mask to set
    :rtype: MulticastCommand
    """
    return SPIFRegister.DIST_MASK_BASE.cmd(mask, index)


def set_distiller_mask_delayed(index, mask_func):
    """ Get a command to set the mask of the distiller of the output via SPIF.
        This tells SPIF which bits to use from the key in the 32-bit output for
        each spike received on the given distiller channel, defined by the
        peripheral routes in the SpiNNaker FPGA.

    :param int index: The index of the channel to set (0-5)
    :param func(int)->int mask_func:
        The function to call to set the mask - takes index as argument
    :rtype: MulticastCommand
    """
    return SPIFRegister.DIST_MASK_BASE.delayed_command(mask_func, index)


def set_distiller_shift(index, shift):
    """ Get a command to set the shift of the distiller of the output via SPIF.
        This tells SPIF how much to shift the key after masking but before
        applying the distiller key.

    :param int index: The index of the channel to set (0-5)
    :param int shift: The shift to set
    :rtype: MulticastCommand
    """
    return SPIFRegister.DIST_SHIFT_BASE.cmd(shift, index)


class _DelayedMultiCastCommand(MultiCastCommand):
    """
    A command where the getting of the payload is delayed.
    """
    __slots__ = ["__get_payload", "__index"]

    def __init__(self, key, get_payload, repeat, delay_between_repeats, index):
        """
        :param int key: The key to send
        :param callable(int)->int get_payload:
            A function to call that returns a payload
        :param int repeat: The number of times to repeat the command
        :param int delay_between_repeats: The delay between the repeats
        :param int index: The index to pass to get_payload when called
        """
        super().__init__(
            key, repeat=repeat, delay_between_repeats=delay_between_repeats)
        self.__get_payload = get_payload
        self.__index = index

    @property
    @overrides(MultiCastCommand.payload)
    def payload(self):
        return self.__get_payload(self.__index)

    @property
    @overrides(MultiCastCommand.is_payload)
    def is_payload(self):
        return True


class SpiNNFPGARegister(IntEnum):
    """
    The register offsets on the SpiNNaker FPGAs for devices.
    """

    #: The base key which identifies packets to send out to the peripheral
    # (deprecated - use XP_KEY_0)
    P_KEY = 2

    #: The mask which identifies packets to send out to the peripheral
    # (deprecated - use XP_MASK_0)
    P_MASK = 3

    #: The base key which identifies packets to write to the FPGA registers
    LC_KEY = 12

    #: The mask which identifies packets to write to the FPGA registers
    LC_MASK = 13

    #: The base key which identifies packets to write to the peripheral
    #: registers
    RC_KEY = 14

    #: The mask which identifies packets to write to the peripheral registers
    RC_MASK = 15

    #: The register to write to to stop the sending of data from the peripheral
    #: to SpiNNaker
    STOP = 16

    #: The register to write to to start the sending of data from the
    #: peripheral to SpiNNaker
    START = 17

    #: The base of the keys that can be sent out of SpiNNaker (up to 6)
    XP_KEY_BASE = 32

    #: The base of the masks that can be sent out of SpiNNake (up to 6)
    XP_MASK_BASE = 48

    def cmd(self, payload=None, index=0):
        """
        Make a command to send to the FPGA to set a register value.

        :param payload:
            The payload to use in the command, or `None` for no payload
        :type payload: int or None
        :param int index:
            The index of the register to send to when there are multiple
            registers starting from a base
        :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
        """
        return MultiCastCommand(
            _LC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
            delay_between_repeats=_DELAY_BETWEEN_REPEATS)

    def delayed_command(self, get_payload, index=0):
        """
        Make a command to send to the FPGA to set a register value,
        where the value itself is currently unknown.

        :param callable(int)->int get_payload:
            A function to call to get the payload later, passing in the index
        :param int index:
            The index of the register to send to when there are multiple
            registers starting from a base
        :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
        """
        return _DelayedMultiCastCommand(
            _LC_KEY + self.value + index, get_payload, repeat=_REPEATS,
            delay_between_repeats=_DELAY_BETWEEN_REPEATS, index=index)


def set_xp_key(index, key):
    """ Get a command to set the key of the output via the FPGA.
        This tells the FPGA to route this key to the external device.

    :param int index: The index of the channel to set (0-5)
    :param int key: The key to set
    :rtype: MulticastCommand
    """
    return SpiNNFPGARegister.XP_KEY_BASE.cmd(key, index)


def set_xp_key_delayed(index, key_func):
    """ Get a command to set the key of the output via the FPGA later.
        This tells the FPGA to route this key to the external device.

    :param int index: The index of the channel to set (0-5)
    :param callable(int)->int key_func: The function to call to get the key
    :rtype: MulticastCommand
    """
    return SpiNNFPGARegister.XP_KEY_BASE.delayed_command(key_func, index)


def set_xp_mask(index, mask):
    """ Get a command to set the mask the output via the FPGA.
        This tells the FPGA to route keys after using this mask to the external
        device.

    :param int index: The index of the channel to set (0-5)
    :param int mask: The mask to set
    :rtype: MulticastCommand
    """
    return SpiNNFPGARegister.XP_MASK_BASE.cmd(mask, index)


def set_xp_mask_delayed(index, mask_func):
    """ Get a command to set the mask of the output via the FPGA later.
        This tells the FPGA to route keys after using this mask to the external
        device.

    :param int index: The index of the channel to set (0-5)
    :param callable(int)->int mask_func: The function to call to get the mask
    :rtype: MulticastCommand
    """
    return SpiNNFPGARegister.XP_MASK_BASE.delayed_command(mask_func, index)

1	# Copyright (c) 2022 The University of Manchester
2	#
3	# Licensed under the Apache License, Version 2.0 (the "License");
4	# you may not use this file except in compliance with the License.
5	# You may obtain a copy of the License at
6	#
7	# https://www.apache.org/licenses/LICENSE-2.0
8	#
9	# Unless required by applicable law or agreed to in writing, software
10	# distributed under the License is distributed on an "AS IS" BASIS,
11	# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12	# See the License for the specific language governing permissions and
13	# limitations under the License.
14	"""	1✔
15	Devices connected to the SpiNNaker peripheral interface (`SPIF`_).
16
17	.. _SPIF: https://github.com/SpiNNakerManchester/spif
18
19	"""
20
21	from enum import IntEnum	1✔
22	from spinn_front_end_common.utility_models import MultiCastCommand	1✔
23	from spinn_utilities.overrides import overrides	1✔
24
25	_REPEATS = 2	1✔
26	_DELAY_BETWEEN_REPEATS = 1	1✔
27
28	#: Base key to send packets to SpiNNaker FPGA (add register offset)
29	_LC_KEY = 0xFFFFFE00	1✔
30
31	#: Base key to send packets to SPIF (add register offset)
32	_RC_KEY = 0xFFFFFF00	1✔
33
34	#: The number of pipes
35	N_PIPES = 2	1✔
36
37	#: The number of fields supported for each pipe
38	N_FIELDS = 4	1✔
39
40	#: The number of filters supported for each pipe
41	N_FILTERS = 8	1✔
42
43	#: The number of FPGA inputs per pipe
44	#:
45	#: .. note::
46	#: The 16 inputs are not actually separated in the hardware,
47	#: but a logical separation per pipe is useful.
48	N_INPUTS = 8	1✔
49
50	#: SPIF is always connected to FPGA 0
51	SPIF_FPGA_ID = 0	1✔
52
53	#: SPIF always outputs to FPGA link 15 on FPGA 0
54	SPIF_OUTPUT_FPGA_LINK = 15	1✔
55
56	#: SPIF always gets input from odd links on FPGA 0 (1, 3, 5, 7, 9, 11, 13, 15)
57	SPIF_INPUT_FPGA_LINKS = range(1, 16, 2)	1✔
58
59
60	class SPIFRegister(IntEnum):	1✔
61	"""
62	The register offsets on a SPIF device.
63	"""
64	#: The key to send messages back when requested
65	REPLY_KEY = 2	1✔
66
67	#: The input key register base (8 inputs per pipe)
68	IR_KEY_BASE = 16	1✔
69
70	#: The input mask register base (8 inputs per pipe)
71	IR_MASK_BASE = 32	1✔
72
73	#: The input route register base (8 inputs per pipe)
74	IR_ROUTE_BASE = 48	1✔
75
76	#: The output peripheral packet count register
77	OUT_PERIPH_PKT_CNT = 64	1✔
78
79	#: The configuration packet count register
80	CONFIG_PKT_CNT = 65	1✔
81
82	#: The dropped packet count register
83	DROPPED_PKT_CNT = 66	1✔
84
85	#: The input peripheral packet count register
86	IN_PERIPH_PKT_CNT = 67	1✔
87
88	#: The output mapper key base register (2 pipes)
89	MP_KEY_BASE = 80	1✔
90
91	#: The output mapper field mask base register (4 fields per pipe)
92	MP_FLD_MASK_BASE = 96	1✔
93
94	#: The output mapper field shift base register (4 fields per pipe)
95	MP_FLD_SHIFT_BASE = 112	1✔
96
97	#: The output mapper field limit base register (4 fields per pipe)
98	MP_FLD_LIMIT_BASE = 128	1✔
99
100	#: The filter value base register (8 filters per pipe)
101	FL_VALUE_BASE = 144	1✔
102
103	#: The filter mask base register (8 filters per pipe)
104	FL_MASK_BASE = 176	1✔
105
106	# The distiller key base register (6 distillers)
107	DIST_KEY_BASE = 208	1✔
108
109	# The distiller key mask register (6 distillers)
110	DIST_MASK_BASE = 224	1✔
111
112	# The distiller key shift register (6 distillers)
113	DIST_SHIFT_BASE = 240	1✔
114
115	def cmd(self, payload=None, index=0):	1✔
116	"""
117	Make a command to send to a SPIF device to set a register value.
118
119	:param payload:
120	The payload to use in the command, or `None` for no payload
121	:type payload: int or None
122	:param int index:
123	The index of the register to send to when there are multiple
124	registers starting from a base
125	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
126	"""
127	return MultiCastCommand(	×
128	_RC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
129	delay_between_repeats=_DELAY_BETWEEN_REPEATS)
130
131	def delayed_command(self, get_payload, index=0):	1✔
132	""" Make a command to send to a SPIF device to set a register value,
133	where the value itself is currently unknown
134
135	:param func()->int get_payload:
136	A function to call to get the payload later
137	:param int index:
138	The index of the register to use when using a multi-indexed
139	register (default is 0 which works for all registers)
140	:rtype: MultiCastCommand
141	"""
NEW 142	return _DelayedMultiCastCommand(	×
143	_RC_KEY + self.value + index, get_payload, repeat=_REPEATS,
144	delay_between_repeats=_DELAY_BETWEEN_REPEATS, index=index)
145
146
147	def set_mapper_key(pipe, key):	1✔
148	"""
149	Get a command to set the output base key for packets from SPIF. This
150	will be added to the keys determined by the mapper output.
151
152	:param int pipe: The SPIF pipe to set the key of (0-1)
153	:param int key: The output key to set
154	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
155	"""
156	return SPIFRegister.MP_KEY_BASE.cmd(key, pipe)	×
157
158
159	def set_field_mask(pipe, index, mask):	1✔
160	"""
161	Get a command to set the mask of a mapper field on SPIF. This masks
162	off the bits of the field from the incoming UDP or USB packet values
163	(which are 32-bits each).
164
165	:param int pipe: The SPIF pipe to set the mask of (0-1)
166	:param int index: The index of the field to set (0-3)
167	:param int mask: The mask to set
168	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
169	"""
170	return SPIFRegister.MP_FLD_MASK_BASE.cmd(mask, (pipe * N_FIELDS) + index)	×
171
172
173	def set_field_shift(pipe, index, shift):	1✔
174	"""
175	Get a command to set the shift of a mapper field on SPIF. This shifts
176	the masked bits of the field from the incoming UDP or USB packet values
177	(which are 32-bits each).
178
179	:param int pipe: The SPIF pipe to set the shift of (0-1)
180	:param int index: The index of the field to set (0-3)
181	:param int shift:
182	The shift value to set (0-31); positive = right, negative = left
183	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
184	"""
185	return SPIFRegister.MP_FLD_SHIFT_BASE.cmd(	×
186	shift, (pipe * N_FIELDS) + index)
187
188
189	def set_field_limit(pipe, index, limit):	1✔
190	"""
191	Get a command to set the limit of a mapper field on SPIF. This sets
192	a limit on the value of the field after shifting and masking.
193
194	:param int pipe: The SPIF pipe to set the limit of (0-1)
195	:param int index: The index of the field to set (0-3)
196	:param int limit: The maximum value of the field
197	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
198	"""
199	return SPIFRegister.MP_FLD_LIMIT_BASE.cmd(	×
200	limit, (pipe * N_FIELDS) + index)
201
202
203	def set_filter_value(pipe, index, value):	1✔
204	"""
205	Get a command to set the value of a filter of SPIF. This will drop
206	input events from the UDP or USB packets where filter value ==
207	filter mask & event value.
208
209	:param int pipe: The SPIF pipe to set the filter of (0-1)
210	:param int index: The index of the filter to set (0-7)
211	:param int value: The filter value to set
212	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
213	"""
214	return SPIFRegister.FL_VALUE_BASE.cmd(	×
215	value, (pipe * N_FILTERS) + index)
216
217
218	def set_filter_mask(pipe, index, mask):	1✔
219	"""
220	Get a command to set the mask of a filter of SPIF. This will drop
221	input events from the UDP or USB packets where filter value ==
222	filter mask & event value.
223
224	:param int pipe: The SPIF pipe to set the filter of (0-1)
225	:param int index: The index of the filter to set (0-7)
226	:param int mask: The filter mask to set
227	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
228	"""
229	return SPIFRegister.FL_MASK_BASE.cmd(	×
230	mask, (pipe * N_FILTERS) + index)
231
232
233	def set_input_key(pipe, index, key):	1✔
234	"""
235	Get a command to set the key of the FPGA input of SPIF. This tells
236	SPIF how to route the incoming packets after they have been assembled
237	by the mapper; when incoming key & input mask == input_key, the packet
238	will be routed to input_route.
239
240	:param int pipe: The SPIF pipe to set the input of (0-1)
241	:param int index: The index of the input to set (0-7)
242	:param int key: The key to set
243	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
244	"""
245	return SPIFRegister.IR_KEY_BASE.cmd(key, (pipe * N_INPUTS) + index)	×
246
247
248	def set_input_mask(pipe, index, mask):	1✔
249	"""
250	Get a command to set the mask of the FPGA input of SPIF. This tells
251	SPIF how to route the incoming packets after they have been assembled
252	by the mapper; when incoming key & input mask == input_key, the packet
253	will be routed to input_route.
254
255	:param int pipe: The SPIF pipe to set the input of (0-1)
256	:param int index: The index of the input to set (0-7)
257	:param int mask: The mask to set
258	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
259	"""
260	return SPIFRegister.IR_MASK_BASE.cmd(mask, (pipe * N_INPUTS) + index)	×
261
262
263	def set_input_route(pipe, index, route):	1✔
264	"""
265	Get a command to set the route of the FPGA input of SPIF. This tells
266	SPIF how to route the incoming packets after they have been assembled
267	by the mapper; when incoming key & input mask == input_key, the packet
268	will be routed to input_route.
269
270	.. note::
271	route 0 refers to FPGA link 15, 1 to 13 and so on in twos.
272
273	:param int pipe: The SPIF pipe to set the input of (0-1)
274	:param int index: The index of the input to set (0-7)
275	:param int route: The route to set
276	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
277	"""
278	return SPIFRegister.IR_ROUTE_BASE.cmd(route, (pipe * N_INPUTS) + index)	×
279
280
281	def set_distiller_key(index, key):	1✔
282	""" Get a command to set the key of the distiller of the output via SPIF.
283	This tells SPIF which bits to put at the top of the 32-bit output for
284	each spike received on the given distiller channel, defined by the
285	peripheral routes in the SpiNNaker FPGA.
286
287	:param int index: The index of the channel to set (0-5)
288	:param int key: The key to set
289	:rtype: MulticastCommand
290	"""
NEW 291	return SPIFRegister.DIST_KEY_BASE.cmd(key, index)	×
292
293
294	def set_distiller_mask(index, mask):	1✔
295	""" Get a command to set the mask of the distiller of the output via SPIF.
296	This tells SPIF which bits to use from the key in the 32-bit output for
297	each spike received on the given distiller channel, defined by the
298	peripheral routes in the SpiNNaker FPGA.
299
300	:param int index: The index of the channel to set (0-5)
301	:param int mask: The mask to set
302	:rtype: MulticastCommand
303	"""
NEW 304	return SPIFRegister.DIST_MASK_BASE.cmd(mask, index)	×
305
306
307	def set_distiller_mask_delayed(index, mask_func):	1✔
308	""" Get a command to set the mask of the distiller of the output via SPIF.
309	This tells SPIF which bits to use from the key in the 32-bit output for
310	each spike received on the given distiller channel, defined by the
311	peripheral routes in the SpiNNaker FPGA.
312
313	:param int index: The index of the channel to set (0-5)
314	:param func(int)->int mask_func:
315	The function to call to set the mask - takes index as argument
316	:rtype: MulticastCommand
317	"""
NEW 318	return SPIFRegister.DIST_MASK_BASE.delayed_command(mask_func, index)	×
319
320
321	def set_distiller_shift(index, shift):	1✔
322	""" Get a command to set the shift of the distiller of the output via SPIF.
323	This tells SPIF how much to shift the key after masking but before
324	applying the distiller key.
325
326	:param int index: The index of the channel to set (0-5)
327	:param int shift: The shift to set
328	:rtype: MulticastCommand
329	"""
NEW 330	return SPIFRegister.DIST_SHIFT_BASE.cmd(shift, index)	×
331
332
333	class _DelayedMultiCastCommand(MultiCastCommand):	1✔
334	"""
335	A command where the getting of the payload is delayed.
336	"""
337	__slots__ = ["__get_payload", "__index"]	1✔
338
339	def __init__(self, key, get_payload, repeat, delay_between_repeats, index):	1✔
340	"""
341	:param int key: The key to send
342	:param callable(int)->int get_payload:
343	A function to call that returns a payload
344	:param int repeat: The number of times to repeat the command
345	:param int delay_between_repeats: The delay between the repeats
346	:param int index: The index to pass to get_payload when called
347	"""
348	super().__init__(	×
349	key, repeat=repeat, delay_between_repeats=delay_between_repeats)
350	self.__get_payload = get_payload	×
NEW 351	self.__index = index	×
352
353	@property	1✔
354	@overrides(MultiCastCommand.payload)	1✔
355	def payload(self):	1✔
NEW 356	return self.__get_payload(self.__index)	×
357
358	@property	1✔
359	@overrides(MultiCastCommand.is_payload)	1✔
360	def is_payload(self):	1✔
361	return True	×
362
363
364	class SpiNNFPGARegister(IntEnum):	1✔
365	"""
366	The register offsets on the SpiNNaker FPGAs for devices.
367	"""
368
369	#: The base key which identifies packets to send out to the peripheral
370	# (deprecated - use XP_KEY_0)
371	P_KEY = 2	1✔
372
373	#: The mask which identifies packets to send out to the peripheral
374	# (deprecated - use XP_MASK_0)
375	P_MASK = 3	1✔
376
377	#: The base key which identifies packets to write to the FPGA registers
378	LC_KEY = 12	1✔
379
380	#: The mask which identifies packets to write to the FPGA registers
381	LC_MASK = 13	1✔
382
383	#: The base key which identifies packets to write to the peripheral
384	#: registers
385	RC_KEY = 14	1✔
386
387	#: The mask which identifies packets to write to the peripheral registers
388	RC_MASK = 15	1✔
389
390	#: The register to write to to stop the sending of data from the peripheral
391	#: to SpiNNaker
392	STOP = 16	1✔
393
394	#: The register to write to to start the sending of data from the
395	#: peripheral to SpiNNaker
396	START = 17	1✔
397
398	#: The base of the keys that can be sent out of SpiNNaker (up to 6)
399	XP_KEY_BASE = 32	1✔
400
401	#: The base of the masks that can be sent out of SpiNNake (up to 6)
402	XP_MASK_BASE = 48	1✔
403
404	def cmd(self, payload=None, index=0):	1✔
405	"""
406	Make a command to send to the FPGA to set a register value.
407
408	:param payload:
409	The payload to use in the command, or `None` for no payload
410	:type payload: int or None
411	:param int index:
412	The index of the register to send to when there are multiple
413	registers starting from a base
414	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
415	"""
416	return MultiCastCommand(	×
417	_LC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
418	delay_between_repeats=_DELAY_BETWEEN_REPEATS)
419
420	def delayed_command(self, get_payload, index=0):	1✔
421	"""
422	Make a command to send to the FPGA to set a register value,
423	where the value itself is currently unknown.
424
425	:param callable(int)->int get_payload:
426	A function to call to get the payload later, passing in the index
427	:param int index:
428	The index of the register to send to when there are multiple
429	registers starting from a base
430	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
431	"""
432	return _DelayedMultiCastCommand(	×
433	_LC_KEY + self.value + index, get_payload, repeat=_REPEATS,
434	delay_between_repeats=_DELAY_BETWEEN_REPEATS, index=index)
435
436
437	def set_xp_key(index, key):	1✔
438	""" Get a command to set the key of the output via the FPGA.
439	This tells the FPGA to route this key to the external device.
440
441	:param int index: The index of the channel to set (0-5)
442	:param int key: The key to set
443	:rtype: MulticastCommand
444	"""
NEW 445	return SpiNNFPGARegister.XP_KEY_BASE.cmd(key, index)	×
446
447
448	def set_xp_key_delayed(index, key_func):	1✔
449	""" Get a command to set the key of the output via the FPGA later.
450	This tells the FPGA to route this key to the external device.
451
452	:param int index: The index of the channel to set (0-5)
453	:param callable(int)->int key_func: The function to call to get the key
454	:rtype: MulticastCommand
455	"""
NEW 456	return SpiNNFPGARegister.XP_KEY_BASE.delayed_command(key_func, index)	×
457
458
459	def set_xp_mask(index, mask):	1✔
460	""" Get a command to set the mask the output via the FPGA.
461	This tells the FPGA to route keys after using this mask to the external
462	device.
463
464	:param int index: The index of the channel to set (0-5)
465	:param int mask: The mask to set
466	:rtype: MulticastCommand
467	"""
NEW 468	return SpiNNFPGARegister.XP_MASK_BASE.cmd(mask, index)	×
469
470
471	def set_xp_mask_delayed(index, mask_func):	1✔
472	""" Get a command to set the mask of the output via the FPGA later.
473	This tells the FPGA to route keys after using this mask to the external
474	device.
475
476	:param int index: The index of the channel to set (0-5)
477	:param callable(int)->int mask_func: The function to call to get the mask
478	:rtype: MulticastCommand
479	"""
NEW 480	return SpiNNFPGARegister.XP_MASK_BASE.delayed_command(mask_func, index)	×

SpiNNakerManchester / sPyNNaker / 6799259904

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