6797134016

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Pull #1408

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rowleya

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Call the function only later!

Pull Request Pull Request #1408: Spif Multi Output

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/spynnaker/pyNN/external_devices_models/spif_devices.py

# Copyright (c) 2022 The University of Manchester
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""
Devices connected to the SpiNNaker peripheral interface (`SPIF`_).

.. _SPIF: https://github.com/SpiNNakerManchester/spif

"""

from enum import IntEnum
from spinn_front_end_common.utility_models import MultiCastCommand
from spinn_utilities.overrides import overrides

_REPEATS = 2
_DELAY_BETWEEN_REPEATS = 1

#: Base key to send packets to SpiNNaker FPGA (add register offset)
_LC_KEY = 0xFFFFFE00

#: Base key to send packets to SPIF (add register offset)
_RC_KEY = 0xFFFFFF00

#: The number of pipes
N_PIPES = 2

#: The number of fields supported for each pipe
N_FIELDS = 4

#: The number of filters supported for each pipe
N_FILTERS = 8

#: The number of FPGA inputs per pipe
#:
#: .. note::
#:     The 16 inputs are not actually separated in the hardware,
#:     but a logical separation per pipe is useful.
N_INPUTS = 8

#: SPIF is always connected to FPGA 0
SPIF_FPGA_ID = 0

#: SPIF always outputs to FPGA link 15 on FPGA 0
SPIF_OUTPUT_FPGA_LINK = 15

#: SPIF always gets input from odd links on FPGA 0 (1, 3, 5, 7, 9, 11, 13, 15)
SPIF_INPUT_FPGA_LINKS = range(1, 16, 2)


class SPIFRegister(IntEnum):
    """
    The register offsets on a SPIF device.
    """
    #: The key to send messages back when requested
    REPLY_KEY = 2

    #: The input key register base (8 inputs per pipe)
    IR_KEY_BASE = 16

    #: The input mask register base (8 inputs per pipe)
    IR_MASK_BASE = 32

    #: The input route register base (8 inputs per pipe)
    IR_ROUTE_BASE = 48

    #: The output peripheral packet count register
    OUT_PERIPH_PKT_CNT = 64

    #: The configuration packet count register
    CONFIG_PKT_CNT = 65

    #: The dropped packet count register
    DROPPED_PKT_CNT = 66

    #: The input peripheral packet count register
    IN_PERIPH_PKT_CNT = 67

    #: The output mapper key base register (2 pipes)
    MP_KEY_BASE = 80

    #: The output mapper field mask base register (4 fields per pipe)
    MP_FLD_MASK_BASE = 96

    #: The output mapper field shift base register (4 fields per pipe)
    MP_FLD_SHIFT_BASE = 112

    #: The output mapper field limit base register (4 fields per pipe)
    MP_FLD_LIMIT_BASE = 128

    #: The filter value base register (8 filters per pipe)
    FL_VALUE_BASE = 144

    #: The filter mask base register (8 filters per pipe)
    FL_MASK_BASE = 176

    def cmd(self, payload=None, index=0):
        """
        Make a command to send to a SPIF device to set a register value.

        :param payload:
            The payload to use in the command, or `None` for no payload
        :type payload: int or None
        :param int index:
            The index of the register to send to when there are multiple
            registers starting from a base
        :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
        """
        return MultiCastCommand(
            _RC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
            delay_between_repeats=_DELAY_BETWEEN_REPEATS)


def set_mapper_key(pipe, key):
    """
    Get a command to set the output base key for packets from SPIF.  This
    will be added to the keys determined by the mapper output.

    :param int pipe: The SPIF pipe to set the key of (0-1)
    :param int key: The output key to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_KEY_BASE.cmd(key, pipe)


def set_field_mask(pipe, index, mask):
    """
    Get a command to set the mask of a mapper field on SPIF.  This masks
    off the bits of the field from the incoming UDP or USB packet values
    (which are 32-bits each).

    :param int pipe: The SPIF pipe to set the mask of (0-1)
    :param int index: The index of the field to set (0-3)
    :param int mask: The mask to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_FLD_MASK_BASE.cmd(mask, (pipe * N_FIELDS) + index)


def set_field_shift(pipe, index, shift):
    """
    Get a command to set the shift of a mapper field on SPIF.  This shifts
    the masked bits of the field from the incoming UDP or USB packet values
    (which are 32-bits each).

    :param int pipe: The SPIF pipe to set the shift of (0-1)
    :param int index: The index of the field to set (0-3)
    :param int shift:
        The shift value to set (0-31); positive = right, negative = left
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_FLD_SHIFT_BASE.cmd(
        shift, (pipe * N_FIELDS) + index)


def set_field_limit(pipe, index, limit):
    """
    Get a command to set the limit of a mapper field on SPIF.  This sets
    a limit on the value of the field after shifting and masking.

    :param int pipe: The SPIF pipe to set the limit of (0-1)
    :param int index: The index of the field to set (0-3)
    :param int limit: The maximum value of the field
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.MP_FLD_LIMIT_BASE.cmd(
        limit, (pipe * N_FIELDS) + index)


def set_filter_value(pipe, index, value):
    """
    Get a command to set the value of a filter of SPIF.  This will drop
    input events from the UDP or USB packets where filter value ==
    filter mask & event value.

    :param int pipe: The SPIF pipe to set the filter of (0-1)
    :param int index: The index of the filter to set (0-7)
    :param int value: The filter value to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.FL_VALUE_BASE.cmd(
        value, (pipe * N_FILTERS) + index)


def set_filter_mask(pipe, index, mask):
    """
    Get a command to set the mask of a filter of SPIF.  This will drop
    input events from the UDP or USB packets where filter value ==
    filter mask & event value.

    :param int pipe: The SPIF pipe to set the filter of (0-1)
    :param int index: The index of the filter to set (0-7)
    :param int mask: The filter mask to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.FL_MASK_BASE.cmd(
        mask, (pipe * N_FILTERS) + index)


def set_input_key(pipe, index, key):
    """
    Get a command to set the key of the FPGA input of SPIF.  This tells
    SPIF how to route the incoming packets after they have been assembled
    by the mapper; when incoming key & input mask == input_key, the packet
    will be routed to input_route.

    :param int pipe: The SPIF pipe to set the input of (0-1)
    :param int index: The index of the input to set (0-7)
    :param int key: The key to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.IR_KEY_BASE.cmd(key, (pipe * N_INPUTS) + index)


def set_input_mask(pipe, index, mask):
    """
    Get a command to set the mask of the FPGA input of SPIF.  This tells
    SPIF how to route the incoming packets after they have been assembled
    by the mapper; when incoming key & input mask == input_key, the packet
    will be routed to input_route.

    :param int pipe: The SPIF pipe to set the input of (0-1)
    :param int index: The index of the input to set (0-7)
    :param int mask: The mask to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.IR_MASK_BASE.cmd(mask, (pipe * N_INPUTS) + index)


def set_input_route(pipe, index, route):
    """
    Get a command to set the route of the FPGA input of SPIF.  This tells
    SPIF how to route the incoming packets after they have been assembled
    by the mapper; when incoming key & input mask == input_key, the packet
    will be routed to input_route.

    .. note::
        route 0 refers to FPGA link 15, 1 to 13 and so on in twos.

    :param int pipe: The SPIF pipe to set the input of (0-1)
    :param int index: The index of the input to set (0-7)
    :param int route: The route to set
    :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
    """
    return SPIFRegister.IR_ROUTE_BASE.cmd(route, (pipe * N_INPUTS) + index)


class _DelayedMultiCastCommand(MultiCastCommand):
    """
    A command where the getting of the payload is delayed.
    """
    __slots__ = ["__get_payload", "__index"]

    def __init__(self, key, get_payload, repeat, delay_between_repeats, index):
        """
        :param int key: The key to send
        :param callable(int)->int get_payload:
            A function to call that returns a payload
        :param int repeat: The number of times to repeat the command
        :param int delay_between_repeats: The delay between the repeats
        :param int index: The index to pass to get_payload when called
        """
        super().__init__(
            key, repeat=repeat, delay_between_repeats=delay_between_repeats)
        self.__get_payload = get_payload
        self.__index = index

    @property
    @overrides(MultiCastCommand.payload)
    def payload(self):
        return self.__get_payload(self.__index)

    @property
    @overrides(MultiCastCommand.is_payload)
    def is_payload(self):
        return True


class SpiNNFPGARegister(IntEnum):
    """
    The register offsets on the SpiNNaker FPGAs for devices.
    """

    #: The base key which identifies packets to send out to the peripheral
    P_KEY = 2

    #: The mask which identifies packets to send out to the peripheral
    P_MASK = 3

    #: The base key which identifies packets to write to the FPGA registers
    LC_KEY = 12

    #: The mask which identifies packets to write to the FPGA registers
    LC_MASK = 13

    #: The base key which identifies packets to write to the peripheral
    #: registers
    RC_KEY = 14

    #: The mask which identifies packets to write to the peripheral registers
    RC_MASK = 15

    #: The register to write to to stop the sending of data from the peripheral
    #: to SpiNNaker
    STOP = 16

    #: The register to write to to start the sending of data from the
    #: peripheral to SpiNNaker
    START = 17

    #: The base of the keys that can be sent out of SpiNNaker (up to 6)
    XP_KEY_BASE = 32

    #: The base of the masks that can be sent out of SpiNNake (up to 6)
    XP_MASK_BASE = 48

    def cmd(self, payload=None, index=0):
        """
        Make a command to send to the FPGA to set a register value.

        :param payload:
            The payload to use in the command, or `None` for no payload
        :type payload: int or None
        :param int index:
            The index of the register to send to when there are multiple
            registers starting from a base
        :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
        """
        return MultiCastCommand(
            _LC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
            delay_between_repeats=_DELAY_BETWEEN_REPEATS)

    def delayed_command(self, get_payload, index=0):
        """
        Make a command to send to the FPGA to set a register value,
        where the value itself is currently unknown.

        :param callable(int)->int get_payload:
            A function to call to get the payload later, passing in the index
        :param int index:
            The index of the register to send to when there are multiple
            registers starting from a base
        :rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
        """
        return _DelayedMultiCastCommand(
            _LC_KEY + self.value + index, get_payload, repeat=_REPEATS,
            delay_between_repeats=_DELAY_BETWEEN_REPEATS, index=index)

1	# Copyright (c) 2022 The University of Manchester
2	#
3	# Licensed under the Apache License, Version 2.0 (the "License");
4	# you may not use this file except in compliance with the License.
5	# You may obtain a copy of the License at
6	#
7	# https://www.apache.org/licenses/LICENSE-2.0
8	#
9	# Unless required by applicable law or agreed to in writing, software
10	# distributed under the License is distributed on an "AS IS" BASIS,
11	# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12	# See the License for the specific language governing permissions and
13	# limitations under the License.
14	"""	1✔
15	Devices connected to the SpiNNaker peripheral interface (`SPIF`_).
16
17	.. _SPIF: https://github.com/SpiNNakerManchester/spif
18
19	"""
20
21	from enum import IntEnum	1✔
22	from spinn_front_end_common.utility_models import MultiCastCommand	1✔
23	from spinn_utilities.overrides import overrides	1✔
24
25	_REPEATS = 2	1✔
26	_DELAY_BETWEEN_REPEATS = 1	1✔
27
28	#: Base key to send packets to SpiNNaker FPGA (add register offset)
29	_LC_KEY = 0xFFFFFE00	1✔
30
31	#: Base key to send packets to SPIF (add register offset)
32	_RC_KEY = 0xFFFFFF00	1✔
33
34	#: The number of pipes
35	N_PIPES = 2	1✔
36
37	#: The number of fields supported for each pipe
38	N_FIELDS = 4	1✔
39
40	#: The number of filters supported for each pipe
41	N_FILTERS = 8	1✔
42
43	#: The number of FPGA inputs per pipe
44	#:
45	#: .. note::
46	#: The 16 inputs are not actually separated in the hardware,
47	#: but a logical separation per pipe is useful.
48	N_INPUTS = 8	1✔
49
50	#: SPIF is always connected to FPGA 0
51	SPIF_FPGA_ID = 0	1✔
52
53	#: SPIF always outputs to FPGA link 15 on FPGA 0
54	SPIF_OUTPUT_FPGA_LINK = 15	1✔
55
56	#: SPIF always gets input from odd links on FPGA 0 (1, 3, 5, 7, 9, 11, 13, 15)
57	SPIF_INPUT_FPGA_LINKS = range(1, 16, 2)	1✔
58
59
60	class SPIFRegister(IntEnum):	1✔
61	"""
62	The register offsets on a SPIF device.
63	"""
64	#: The key to send messages back when requested
65	REPLY_KEY = 2	1✔
66
67	#: The input key register base (8 inputs per pipe)
68	IR_KEY_BASE = 16	1✔
69
70	#: The input mask register base (8 inputs per pipe)
71	IR_MASK_BASE = 32	1✔
72
73	#: The input route register base (8 inputs per pipe)
74	IR_ROUTE_BASE = 48	1✔
75
76	#: The output peripheral packet count register
77	OUT_PERIPH_PKT_CNT = 64	1✔
78
79	#: The configuration packet count register
80	CONFIG_PKT_CNT = 65	1✔
81
82	#: The dropped packet count register
83	DROPPED_PKT_CNT = 66	1✔
84
85	#: The input peripheral packet count register
86	IN_PERIPH_PKT_CNT = 67	1✔
87
88	#: The output mapper key base register (2 pipes)
89	MP_KEY_BASE = 80	1✔
90
91	#: The output mapper field mask base register (4 fields per pipe)
92	MP_FLD_MASK_BASE = 96	1✔
93
94	#: The output mapper field shift base register (4 fields per pipe)
95	MP_FLD_SHIFT_BASE = 112	1✔
96
97	#: The output mapper field limit base register (4 fields per pipe)
98	MP_FLD_LIMIT_BASE = 128	1✔
99
100	#: The filter value base register (8 filters per pipe)
101	FL_VALUE_BASE = 144	1✔
102
103	#: The filter mask base register (8 filters per pipe)
104	FL_MASK_BASE = 176	1✔
105
106	def cmd(self, payload=None, index=0):	1✔
107	"""
108	Make a command to send to a SPIF device to set a register value.
109
110	:param payload:
111	The payload to use in the command, or `None` for no payload
112	:type payload: int or None
113	:param int index:
114	The index of the register to send to when there are multiple
115	registers starting from a base
116	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
117	"""
118	return MultiCastCommand(	×
119	_RC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
120	delay_between_repeats=_DELAY_BETWEEN_REPEATS)
121
122
123	def set_mapper_key(pipe, key):	1✔
124	"""
125	Get a command to set the output base key for packets from SPIF. This
126	will be added to the keys determined by the mapper output.
127
128	:param int pipe: The SPIF pipe to set the key of (0-1)
129	:param int key: The output key to set
130	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
131	"""
132	return SPIFRegister.MP_KEY_BASE.cmd(key, pipe)	×
133
134
135	def set_field_mask(pipe, index, mask):	1✔
136	"""
137	Get a command to set the mask of a mapper field on SPIF. This masks
138	off the bits of the field from the incoming UDP or USB packet values
139	(which are 32-bits each).
140
141	:param int pipe: The SPIF pipe to set the mask of (0-1)
142	:param int index: The index of the field to set (0-3)
143	:param int mask: The mask to set
144	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
145	"""
146	return SPIFRegister.MP_FLD_MASK_BASE.cmd(mask, (pipe * N_FIELDS) + index)	×
147
148
149	def set_field_shift(pipe, index, shift):	1✔
150	"""
151	Get a command to set the shift of a mapper field on SPIF. This shifts
152	the masked bits of the field from the incoming UDP or USB packet values
153	(which are 32-bits each).
154
155	:param int pipe: The SPIF pipe to set the shift of (0-1)
156	:param int index: The index of the field to set (0-3)
157	:param int shift:
158	The shift value to set (0-31); positive = right, negative = left
159	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
160	"""
161	return SPIFRegister.MP_FLD_SHIFT_BASE.cmd(	×
162	shift, (pipe * N_FIELDS) + index)
163
164
165	def set_field_limit(pipe, index, limit):	1✔
166	"""
167	Get a command to set the limit of a mapper field on SPIF. This sets
168	a limit on the value of the field after shifting and masking.
169
170	:param int pipe: The SPIF pipe to set the limit of (0-1)
171	:param int index: The index of the field to set (0-3)
172	:param int limit: The maximum value of the field
173	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
174	"""
175	return SPIFRegister.MP_FLD_LIMIT_BASE.cmd(	×
176	limit, (pipe * N_FIELDS) + index)
177
178
179	def set_filter_value(pipe, index, value):	1✔
180	"""
181	Get a command to set the value of a filter of SPIF. This will drop
182	input events from the UDP or USB packets where filter value ==
183	filter mask & event value.
184
185	:param int pipe: The SPIF pipe to set the filter of (0-1)
186	:param int index: The index of the filter to set (0-7)
187	:param int value: The filter value to set
188	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
189	"""
190	return SPIFRegister.FL_VALUE_BASE.cmd(	×
191	value, (pipe * N_FILTERS) + index)
192
193
194	def set_filter_mask(pipe, index, mask):	1✔
195	"""
196	Get a command to set the mask of a filter of SPIF. This will drop
197	input events from the UDP or USB packets where filter value ==
198	filter mask & event value.
199
200	:param int pipe: The SPIF pipe to set the filter of (0-1)
201	:param int index: The index of the filter to set (0-7)
202	:param int mask: The filter mask to set
203	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
204	"""
205	return SPIFRegister.FL_MASK_BASE.cmd(	×
206	mask, (pipe * N_FILTERS) + index)
207
208
209	def set_input_key(pipe, index, key):	1✔
210	"""
211	Get a command to set the key of the FPGA input of SPIF. This tells
212	SPIF how to route the incoming packets after they have been assembled
213	by the mapper; when incoming key & input mask == input_key, the packet
214	will be routed to input_route.
215
216	:param int pipe: The SPIF pipe to set the input of (0-1)
217	:param int index: The index of the input to set (0-7)
218	:param int key: The key to set
219	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
220	"""
221	return SPIFRegister.IR_KEY_BASE.cmd(key, (pipe * N_INPUTS) + index)	×
222
223
224	def set_input_mask(pipe, index, mask):	1✔
225	"""
226	Get a command to set the mask of the FPGA input of SPIF. This tells
227	SPIF how to route the incoming packets after they have been assembled
228	by the mapper; when incoming key & input mask == input_key, the packet
229	will be routed to input_route.
230
231	:param int pipe: The SPIF pipe to set the input of (0-1)
232	:param int index: The index of the input to set (0-7)
233	:param int mask: The mask to set
234	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
235	"""
236	return SPIFRegister.IR_MASK_BASE.cmd(mask, (pipe * N_INPUTS) + index)	×
237
238
239	def set_input_route(pipe, index, route):	1✔
240	"""
241	Get a command to set the route of the FPGA input of SPIF. This tells
242	SPIF how to route the incoming packets after they have been assembled
243	by the mapper; when incoming key & input mask == input_key, the packet
244	will be routed to input_route.
245
246	.. note::
247	route 0 refers to FPGA link 15, 1 to 13 and so on in twos.
248
249	:param int pipe: The SPIF pipe to set the input of (0-1)
250	:param int index: The index of the input to set (0-7)
251	:param int route: The route to set
252	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
253	"""
254	return SPIFRegister.IR_ROUTE_BASE.cmd(route, (pipe * N_INPUTS) + index)	×
255
256
257	class _DelayedMultiCastCommand(MultiCastCommand):	1✔
258	"""
259	A command where the getting of the payload is delayed.
260	"""
261	__slots__ = ["__get_payload", "__index"]	1✔
262
263	def __init__(self, key, get_payload, repeat, delay_between_repeats, index):	1✔
264	"""
265	:param int key: The key to send
266	:param callable(int)->int get_payload:
267	A function to call that returns a payload
268	:param int repeat: The number of times to repeat the command
269	:param int delay_between_repeats: The delay between the repeats
270	:param int index: The index to pass to get_payload when called
271	"""
272	super().__init__(	×
273	key, repeat=repeat, delay_between_repeats=delay_between_repeats)
274	self.__get_payload = get_payload	×
NEW 275	self.__index = index	×
276
277	@property	1✔
278	@overrides(MultiCastCommand.payload)	1✔
279	def payload(self):	1✔
NEW 280	return self.__get_payload(self.__index)	×
281
282	@property	1✔
283	@overrides(MultiCastCommand.is_payload)	1✔
284	def is_payload(self):	1✔
285	return True	×
286
287
288	class SpiNNFPGARegister(IntEnum):	1✔
289	"""
290	The register offsets on the SpiNNaker FPGAs for devices.
291	"""
292
293	#: The base key which identifies packets to send out to the peripheral
294	P_KEY = 2	1✔
295
296	#: The mask which identifies packets to send out to the peripheral
297	P_MASK = 3	1✔
298
299	#: The base key which identifies packets to write to the FPGA registers
300	LC_KEY = 12	1✔
301
302	#: The mask which identifies packets to write to the FPGA registers
303	LC_MASK = 13	1✔
304
305	#: The base key which identifies packets to write to the peripheral
306	#: registers
307	RC_KEY = 14	1✔
308
309	#: The mask which identifies packets to write to the peripheral registers
310	RC_MASK = 15	1✔
311
312	#: The register to write to to stop the sending of data from the peripheral
313	#: to SpiNNaker
314	STOP = 16	1✔
315
316	#: The register to write to to start the sending of data from the
317	#: peripheral to SpiNNaker
318	START = 17	1✔
319
320	#: The base of the keys that can be sent out of SpiNNaker (up to 6)
321	XP_KEY_BASE = 32	1✔
322
323	#: The base of the masks that can be sent out of SpiNNake (up to 6)
324	XP_MASK_BASE = 48	1✔
325
326	def cmd(self, payload=None, index=0):	1✔
327	"""
328	Make a command to send to the FPGA to set a register value.
329
330	:param payload:
331	The payload to use in the command, or `None` for no payload
332	:type payload: int or None
333	:param int index:
334	The index of the register to send to when there are multiple
335	registers starting from a base
336	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
337	"""
338	return MultiCastCommand(	×
339	_LC_KEY + self.value + index, payload, time=None, repeat=_REPEATS,
340	delay_between_repeats=_DELAY_BETWEEN_REPEATS)
341
342	def delayed_command(self, get_payload, index=0):	1✔
343	"""
344	Make a command to send to the FPGA to set a register value,
345	where the value itself is currently unknown.
346
347	:param callable(int)->int get_payload:
348	A function to call to get the payload later, passing in the index
349	:param int index:
350	The index of the register to send to when there are multiple
351	registers starting from a base
352	:rtype: ~spinn_front_end_common.utility_models.MultiCastCommand
353	"""
354	return _DelayedMultiCastCommand(	×
355	_LC_KEY + self.value + index, get_payload, repeat=_REPEATS,
356	delay_between_repeats=_DELAY_BETWEEN_REPEATS, index=index)

SpiNNakerManchester / sPyNNaker / 6797134016

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