6747815873

Committed 03 Nov 2023 04:28PM UTC coverage: 76.813% (-1.8%) from 78.646%

Build # 6747815873

Build Type

Pull #1198

github

Committed by

web-flow

Commit Message

Merge 0d6db567b into ad2cde1e0

Pull Request Pull Request #1198: Add overloads for new atomic and barrier API to numba_dpex.experimental module

Run Details

1134 of 1769 branches covered (0.0%)

Branch coverage included in aggregate %.

188 of 372 new or added lines in 14 files covered. (50.54%)

31 existing lines in 4 files now uncovered.

5233 of 6520 relevant lines covered (80.26%)

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98.31

/numba_dpex/core/codegen.py

# SPDX-FileCopyrightText: 2020 - 2023 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0

import logging

from llvmlite import binding as ll
from llvmlite import ir as llvmir
from numba.core import utils
from numba.core.codegen import CPUCodegen, CPUCodeLibrary

from numba_dpex import config

SPIR_TRIPLE = {32: " spir-unknown-unknown", 64: "spir64-unknown-unknown"}

SPIR_DATA_LAYOUT = {
    32: (
        "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:"
        "256-v512:512-v1024:1024"
    ),
    64: (
        "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
        "v512:512-v1024:1024"
    ),
}


class SPIRVCodeLibrary(CPUCodeLibrary):
    def _optimize_functions(self, ll_module):
        pass

    def _optimize_final_module(self):
        # Run some lightweight optimization to simplify the module.
        pmb = ll.PassManagerBuilder()

        # Make optimization level depending on config.DPEX_OPT variable
        pmb.opt_level = config.DPEX_OPT
        if config.DPEX_OPT > 2:
            logging.warning(
                "Setting NUMBA_DPEX_OPT greater than 2 known to cause issues "
                + "related to very aggressive optimizations that leads to "
                + "broken code."
            )

        pmb.disable_unit_at_a_time = False
        if config.INLINE_THRESHOLD is not None:
            logging.warning(
                "Setting INLINE_THRESHOLD leads to very aggressive "
                + "optimizations that may produce incorrect binary."
            )
            pmb.inlining_threshold = config.INLINE_THRESHOLD
        pmb.disable_unroll_loops = True
        pmb.loop_vectorize = False
        pmb.slp_vectorize = False

        pm = ll.ModulePassManager()
        pmb.populate(pm)
        pm.run(self._final_module)

    def _finalize_specific(self):
        # Fix global naming
        for gv in self._final_module.global_variables:
            if "." in gv.name:
                gv.name = gv.name.replace(".", "_")

    def get_asm_str(self):
        # Return nothing: we can only dump assembler code when it is later
        # generated (in numba_dpex.compiler).
        return None


class JITSPIRVCodegen(CPUCodegen):
    """
    This codegen implementation generates optimized SPIR 2.0
    """

    _library_class = SPIRVCodeLibrary

    def _init(self, llvm_module):
        assert list(llvm_module.global_variables) == [], "Module isn't empty"
        self._data_layout = SPIR_DATA_LAYOUT[utils.MACHINE_BITS]
        self._target_data = ll.create_target_data(self._data_layout)
        self._tm_features = (
            ""  # We need this for caching, not sure about this value for now
        )

    def _create_empty_module(self, name):
        ir_module = llvmir.Module(name)
        ir_module.triple = SPIR_TRIPLE[utils.MACHINE_BITS]
        if self._data_layout:
            ir_module.data_layout = self._data_layout
        return ir_module

    def _module_pass_manager(self):
        raise NotImplementedError

    def _function_pass_manager(self, llvm_module):
        raise NotImplementedError

    def _add_module(self, module):
        pass

1	# SPDX-FileCopyrightText: 2020 - 2023 Intel Corporation
2	#
3	# SPDX-License-Identifier: Apache-2.0
4
5	import logging	1✔
6
7	from llvmlite import binding as ll	1✔
8	from llvmlite import ir as llvmir	1✔
9	from numba.core import utils	1✔
10	from numba.core.codegen import CPUCodegen, CPUCodeLibrary	1✔
11
12	from numba_dpex import config	1✔
13
14	SPIR_TRIPLE = {32: " spir-unknown-unknown", 64: "spir64-unknown-unknown"}	1✔
15
16	SPIR_DATA_LAYOUT = {	1✔
17	32: (
18	"e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:"
19	"256-v512:512-v1024:1024"
20	),
21	64: (
22	"e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
23	"v512:512-v1024:1024"
24	),
25	}
26
27
28	class SPIRVCodeLibrary(CPUCodeLibrary):	1✔
29	def _optimize_functions(self, ll_module):	1✔
30	pass	1✔
31
32	def _optimize_final_module(self):	1✔
33	# Run some lightweight optimization to simplify the module.
34	pmb = ll.PassManagerBuilder()	1✔
35
36	# Make optimization level depending on config.DPEX_OPT variable
37	pmb.opt_level = config.DPEX_OPT	1✔
38	if config.DPEX_OPT > 2:	1✔
39	logging.warning(	1✔
40	"Setting NUMBA_DPEX_OPT greater than 2 known to cause issues "
41	+ "related to very aggressive optimizations that leads to "
42	+ "broken code."
43	)
44
45	pmb.disable_unit_at_a_time = False	1✔
46	if config.INLINE_THRESHOLD is not None:	1✔
47	logging.warning(	1✔
48	"Setting INLINE_THRESHOLD leads to very aggressive "
49	+ "optimizations that may produce incorrect binary."
50	)
51	pmb.inlining_threshold = config.INLINE_THRESHOLD	1✔
52	pmb.disable_unroll_loops = True	1✔
53	pmb.loop_vectorize = False	1✔
54	pmb.slp_vectorize = False	1✔
55
56	pm = ll.ModulePassManager()	1✔
57	pmb.populate(pm)	1✔
58	pm.run(self._final_module)	1✔
59
60	def _finalize_specific(self):	1✔
61	# Fix global naming
62	for gv in self._final_module.global_variables:	1✔
63	if "." in gv.name:	1✔
64	gv.name = gv.name.replace(".", "_")	1✔
65
66	def get_asm_str(self):	1✔
67	# Return nothing: we can only dump assembler code when it is later
68	# generated (in numba_dpex.compiler).
UNCOV 69	return None	×
70
71
72	class JITSPIRVCodegen(CPUCodegen):	1✔
73	"""
74	This codegen implementation generates optimized SPIR 2.0
75	"""
76
77	_library_class = SPIRVCodeLibrary	1✔
78
79	def _init(self, llvm_module):	1✔
80	assert list(llvm_module.global_variables) == [], "Module isn't empty"	1✔
81	self._data_layout = SPIR_DATA_LAYOUT[utils.MACHINE_BITS]	1✔
82	self._target_data = ll.create_target_data(self._data_layout)	1✔
83	self._tm_features = (	1✔
84	"" # We need this for caching, not sure about this value for now
85	)
86
87	def _create_empty_module(self, name):	1✔
88	ir_module = llvmir.Module(name)	1✔
89	ir_module.triple = SPIR_TRIPLE[utils.MACHINE_BITS]	1✔
90	if self._data_layout:	1✔
91	ir_module.data_layout = self._data_layout	1✔
92	return ir_module	1✔
93
94	def _module_pass_manager(self):	1✔
95	raise NotImplementedError
96
97	def _function_pass_manager(self, llvm_module):	1✔
98	raise NotImplementedError
99
100	def _add_module(self, module):	1✔
101	pass	1✔

IntelPython / numba-dpex / 6747815873

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