1934734091

Build # 1934734091

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github

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<a href="https://github.com/OPAE/opae-sdk/commit/<a class=hub.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://git"><a class=hub.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://git"><a class=hub.com/OPAE/opae-sdk/commit/8753285cac03b677dc771238f5519df67b0dff02">8753285ca<a href="https://github.com/OPAE/opae-sdk/commit/8753285cac03b677dc771238f5519df67b0dff02">&quot;&gt;&amp;lt;a href=&amp;quot;https://github.com/OPAE/opae-sdk/commit/&lt;/a&gt;&lt;a class=&quot;double-link&quot; href=&quot;https://github.com/OPAE/opae-sdk/commit/&amp;lt;a class=&amp;quot;double-link&amp;quot; href=&amp;quot;https://git&quot;&gt;&amp;lt;a class=&lt;/a&gt;hub.com/OPAE/opae-sdk/commit/8753285cac03b677dc771238f5519df67b0dff02&quot;&gt;8753285ca&lt;/a&gt;&lt;a href=&quot;https://github.com/OPAE/opae-sdk/commit/8753285cac03b677dc771238f5519df67b0dff02&quot;&gt;&amp;lt;a href=&amp;quot;https://github.com/OPAE/opae-sdk/commit/8753285cac03b677dc771238f5519df6&lt;/a&gt;7b0dff02">&quot;&gt;Merge &lt;/a&gt;&lt;a class=&quot;double-link&quot; href=&quot;https://github.com/OPAE/opae-sdk/commit/&lt;a class=&quot;double-link&quot; href=&quot;https://github.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://github.com/OPAE/opae-sdk/commit/806cc34dd908b9dd59898e1f61e5b43b3731a812">806cc34dd</a><a href="https://github.com/OPAE/opae-sdk/commit/8753285cac03b677dc771238f5519df67b0dff02">&amp;quot;&amp;gt;806cc34dd&amp;lt;/a&amp;gt;&amp;quot;&amp;gt;806cc34dd&amp;lt;/a&amp;gt;&amp;lt;a href=&amp;quot;https://github.com/OPAE/opae-sdk/commit/8753285cac03b677dc771238f5519df67b0df&lt;/a&gt;f02&quot;&gt; into &lt;/a&gt;&lt;a class=&quot;double-link&quot; href=&quot;https://github.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://github.com/OPAE/opae-sdk/commit/042d7fc46">042d7fc46">042d7fc46</a>

Pull Request Pull Request #2508: opae-sdk: fix clang build errors

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/samples/mem_tg/tg_test.h

// Copyright(c) 2022, Intel Corporation
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
#pragma once

#include <unistd.h>

#include "afu_test.h"
#include "mem_tg.h"

using test_afu = opae::afu_test::afu;
using opae::fpga::types::token;

namespace mem_tg {

class tg_test : public test_command
{
public:
    tg_test()
        :tg_exe_(NULL) {
          tg_offset_ = 0x0;
    }
    virtual ~tg_test(){}

    virtual  const char *name() const override
    {
        return "tg_test";
    }

    virtual  const char *description() const override
    {
      return "configure & run mem traffic generator test";
    }

    virtual const char *afu_id() const override
    {
      return AFU_ID;
    }


    // Convert number of transactions to bandwidth (GB/s)
    double bw_calc(uint64_t xfer_bytes, uint64_t num_ticks)
    {
        return (double)(xfer_bytes) / ((1000.0 / (double)tg_exe_->mem_speed_ * (double)num_ticks));
    }

    void tg_perf () {
      uint32_t mem_ch_offset = (tg_exe_->mem_ch_) << 0x3;
      uint64_t num_ticks = tg_exe_->read64(MEM_TG_CLOCKS + mem_ch_offset);
      std::cout << "Mem Clock Cycles: " << std::dec << num_ticks << std::endl;
      uint64_t write_bytes = 64 * (tg_exe_->loop_*tg_exe_->wcnt_*tg_exe_->bcnt_);
      uint64_t read_bytes  = 64 * (tg_exe_->loop_*tg_exe_->rcnt_*tg_exe_->bcnt_);
      std::cout << "Write BW: " << bw_calc(write_bytes,num_ticks) << " GB/s" << std::endl;
      std::cout << "Read BW: "  << bw_calc(read_bytes,num_ticks)  << " GB/s" << std::endl;
    }
  
    bool tg_wait_test_completion ()
    {
        /* Wait for test completion */
        uint32_t           timeout = MEM_TG_TEST_TIMEOUT;

        // poll while active bit is set (channel status = {pass,fail,timeout,active})
        uint32_t tg_status = 0x1;
        tg_status = 0xF&(tg_exe_->read64(MEM_TG_STAT) >> (0x4*(tg_exe_->mem_ch_)));
        while ( tg_status == TG_STATUS_ACTIVE ) {
          tg_status = 0xF&(tg_exe_->read64(MEM_TG_STAT) >> (0x4*(tg_exe_->mem_ch_)));
          usleep(TEST_SLEEP_INVL);
          if (--timeout == 0) {
            std::cout << "TG TEST TIME OUT" << std::endl;
            return false;
          }
        }
        if(tg_status == TG_STATUS_TIMEOUT) {
          std::cout << "TG TIMEOUT" << std::endl;
          return false;
        }
        if (tg_status == TG_STATUS_ERROR) {
          std::cout << "TG ERROR" << std::endl;
          return false;
        }
        std::cout << "TG PASS" << std::endl;
        return true;
    }


    int config_input_options()
    {
        if (!tg_exe_)
            return -1;

        uint64_t mem_capability = tg_exe_->read64(MEM_TG_CTRL);
        if((mem_capability & (0x1 << tg_exe_->mem_ch_)) == 0) {
          std::cerr << "No traffic generator for mem[" << tg_exe_->mem_ch_ << "]" << std::endl;
          return -1;
        } else {
          tg_offset_ = AFU_DFH + (MEM_TG_CFG_OFFSET * (1+tg_exe_->mem_ch_));
        }
        
        tg_exe_->write32(tg_offset_+TG_LOOP_COUNT,  tg_exe_->loop_);
        tg_exe_->write32(tg_offset_+TG_WRITE_COUNT, tg_exe_->wcnt_);
        tg_exe_->write32(tg_offset_+TG_READ_COUNT,  tg_exe_->rcnt_);
        tg_exe_->write32(tg_offset_+TG_BURST_LENGTH, tg_exe_->bcnt_);
        tg_exe_->write32(tg_offset_+TG_SEQ_ADDR_INCR, tg_exe_->stride_);

        // address increment mode
        tg_exe_->write32(tg_offset_+TG_ADDR_MODE_WR, TG_ADDR_SEQ);
        tg_exe_->write32(tg_offset_+TG_ADDR_MODE_RD, TG_ADDR_SEQ);

        return 0;
    }

    // The test state has been configured. Run one test instance.
    int run_mem_test()
    {
        int status = 0;
        
        tg_exe_->logger_->debug("Start Test");

        tg_exe_->write32(tg_offset_+TG_START,0x1);

        if(!tg_wait_test_completion())
          status = -1;

        tg_perf();
        
        return status;
    }


    virtual int run(test_afu *afu, CLI::App *app) override
    {
        (void)app;

        auto d_afu = dynamic_cast<mem_tg*>(afu);
        tg_exe_ = dynamic_cast<mem_tg*>(afu);

        token_ = d_afu->get_token();

        // Read HW details

        if (0 == tg_exe_->mem_speed_) {
          tg_exe_->mem_speed_ = 300;
          std::cout << "Memory channel clock frequency unknown. Assuming "
                    << tg_exe_->mem_speed_ << " MHz." << std::endl;
        }
        else {
            std::cout << "Memory clock from command line: "
                      << tg_exe_->mem_speed_ << " MHz" << std::endl;
        }

        auto ret = config_input_options();
        if (ret != 0) {
            std::cerr << "Failed to configure TG input options" << std::endl;
            return ret;
        }

        return run_mem_test();
    }

protected:
    uint64_t tg_offset_;
    mem_tg *tg_exe_;
    token::ptr_t token_;
};

} // end of namespace mem_tg


1	// Copyright(c) 2022, Intel Corporation
2	//
3	// Redistribution and use in source and binary forms, with or without
4	// modification, are permitted provided that the following conditions are met:
5	//
6	// * Redistributions of source code must retain the above copyright notice,
7	// this list of conditions and the following disclaimer.
8	// * Redistributions in binary form must reproduce the above copyright notice,
9	// this list of conditions and the following disclaimer in the documentation
10	// and/or other materials provided with the distribution.
11	// * Neither the name of Intel Corporation nor the names of its contributors
12	// may be used to endorse or promote products derived from this software
13	// without specific prior written permission.
14	//
15	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16	// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19	// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20	// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21	// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22	// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23	// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24	// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25	// POSSIBILITY OF SUCH DAMAGE.
26	#pragma once
27
28	#include <unistd.h>
29
30	#include "afu_test.h"
31	#include "mem_tg.h"
32
33	using test_afu = opae::afu_test::afu;
34	using opae::fpga::types::token;
35
36	namespace mem_tg {
37
38	class tg_test : public test_command
39	{
40	public:
41	tg_test()	×
42	:tg_exe_(NULL) {	×
43	tg_offset_ = 0x0;	×
44	}	×
45	virtual ~tg_test(){}	×
46
47	virtual const char *name() const override	×
48	{
49	return "tg_test";	×
50	}
51
52	virtual const char *description() const override	×
53	{
54	return "configure & run mem traffic generator test";	×
55	}
56
57	virtual const char *afu_id() const override	×
58	{
59	return AFU_ID;	×
60	}
61
62
63	// Convert number of transactions to bandwidth (GB/s)
64	double bw_calc(uint64_t xfer_bytes, uint64_t num_ticks)	×
65	{
66	return (double)(xfer_bytes) / ((1000.0 / (double)tg_exe_->mem_speed_ * (double)num_ticks));	×
67	}
68
69	void tg_perf () {	×
70	uint32_t mem_ch_offset = (tg_exe_->mem_ch_) << 0x3;	×
71	uint64_t num_ticks = tg_exe_->read64(MEM_TG_CLOCKS + mem_ch_offset);	×
72	std::cout << "Mem Clock Cycles: " << std::dec << num_ticks << std::endl;	×
73	uint64_t write_bytes = 64 * (tg_exe_->loop_tg_exe_->wcnt_tg_exe_->bcnt_);	×
74	uint64_t read_bytes = 64 * (tg_exe_->loop_tg_exe_->rcnt_tg_exe_->bcnt_);	×
75	std::cout << "Write BW: " << bw_calc(write_bytes,num_ticks) << " GB/s" << std::endl;	×
76	std::cout << "Read BW: " << bw_calc(read_bytes,num_ticks) << " GB/s" << std::endl;	×
77	}	×
78
79	bool tg_wait_test_completion ()	×
80	{
81	/* Wait for test completion */
82	uint32_t timeout = MEM_TG_TEST_TIMEOUT;	×
83
84	// poll while active bit is set (channel status = {pass,fail,timeout,active})
85	uint32_t tg_status = 0x1;	×
86	tg_status = 0xF&(tg_exe_->read64(MEM_TG_STAT) >> (0x4*(tg_exe_->mem_ch_)));	×
87	while ( tg_status == TG_STATUS_ACTIVE ) {	×
88	tg_status = 0xF&(tg_exe_->read64(MEM_TG_STAT) >> (0x4*(tg_exe_->mem_ch_)));	×
89	usleep(TEST_SLEEP_INVL);	×
90	if (--timeout == 0) {	×
91	std::cout << "TG TEST TIME OUT" << std::endl;	×
92	return false;	×
93	}
94	}
95	if(tg_status == TG_STATUS_TIMEOUT) {	×
96	std::cout << "TG TIMEOUT" << std::endl;	×
97	return false;	×
98	}
99	if (tg_status == TG_STATUS_ERROR) {	×
100	std::cout << "TG ERROR" << std::endl;	×
101	return false;	×
102	}
103	std::cout << "TG PASS" << std::endl;	×
104	return true;	×
105	}
106
107
108	int config_input_options()	×
109	{
110	if (!tg_exe_)	×
111	return -1;	×
112
113	uint64_t mem_capability = tg_exe_->read64(MEM_TG_CTRL);	×
114	if((mem_capability & (0x1 << tg_exe_->mem_ch_)) == 0) {	×
115	std::cerr << "No traffic generator for mem[" << tg_exe_->mem_ch_ << "]" << std::endl;	×
116	return -1;	×
117	} else {
118	tg_offset_ = AFU_DFH + (MEM_TG_CFG_OFFSET * (1+tg_exe_->mem_ch_));	×
119	}
120
121	tg_exe_->write32(tg_offset_+TG_LOOP_COUNT, tg_exe_->loop_);	×
122	tg_exe_->write32(tg_offset_+TG_WRITE_COUNT, tg_exe_->wcnt_);	×
123	tg_exe_->write32(tg_offset_+TG_READ_COUNT, tg_exe_->rcnt_);	×
124	tg_exe_->write32(tg_offset_+TG_BURST_LENGTH, tg_exe_->bcnt_);	×
125	tg_exe_->write32(tg_offset_+TG_SEQ_ADDR_INCR, tg_exe_->stride_);	×
126
127	// address increment mode
128	tg_exe_->write32(tg_offset_+TG_ADDR_MODE_WR, TG_ADDR_SEQ);	×
129	tg_exe_->write32(tg_offset_+TG_ADDR_MODE_RD, TG_ADDR_SEQ);	×
130
131	return 0;	×
132	}
133
134	// The test state has been configured. Run one test instance.
135	int run_mem_test()	×
136	{
137	int status = 0;	×
138
139	tg_exe_->logger_->debug("Start Test");	×
140
141	tg_exe_->write32(tg_offset_+TG_START,0x1);	×
142
143	if(!tg_wait_test_completion())	×
144	status = -1;	×
145
146	tg_perf();	×
147
148	return status;	×
149	}
150
151
152	virtual int run(test_afu afu, CLI::App app) override	×
153	{
154	(void)app;
155
156	auto d_afu = dynamic_cast<mem_tg*>(afu);	×
157	tg_exe_ = dynamic_cast<mem_tg*>(afu);	×
158
159	token_ = d_afu->get_token();	×
160
161	// Read HW details
162
163	if (0 == tg_exe_->mem_speed_) {	×
164	tg_exe_->mem_speed_ = 300;	×
165	std::cout << "Memory channel clock frequency unknown. Assuming "	×
166	<< tg_exe_->mem_speed_ << " MHz." << std::endl;	×
167	}
168	else {
169	std::cout << "Memory clock from command line: "	×
170	<< tg_exe_->mem_speed_ << " MHz" << std::endl;	×
171	}
172
173	auto ret = config_input_options();	×
174	if (ret != 0) {	×
175	std::cerr << "Failed to configure TG input options" << std::endl;	×
176	return ret;	×
177	}
178
179	return run_mem_test();	×
180	}
181
182	protected:
183	uint64_t tg_offset_;
184	mem_tg *tg_exe_;
185	token::ptr_t token_;
186	};
187
188	} // end of namespace mem_tg
189

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