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Pull Request Pull Request #2424: hssi: support hssi performance

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/samples/hssi/hssi_10g_cmd.h

// Copyright(c) 2020-2021, Intel Corporation
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
#pragma once
#include <iostream>
#include <string>
#include "hssi_cmd.h"

#define CSR_NUM_PACKETS       0x3c00
#define CSR_RANDOM_LENGTH     0x3c01
#define CSR_RANDOM_PAYLOAD    0x3c02
#define CSR_START             0x3c03
#define CSR_STOP              0x3c04
#define CSR_SRC_ADDR0         0x3c05
#define CSR_SRC_ADDR1         0x3c06
#define CSR_DEST_ADDR0        0x3c07
#define CSR_DEST_ADDR1        0x3c08
#define CSR_PACKET_TX_COUNT   0x3c09
#define CSR_RND_SEED0         0x3c0a
#define CSR_RND_SEED1         0x3c0b
#define CSR_RND_SEED2         0x3c0c
#define CSR_PACKET_LENGTH     0x3c0d
#define CSR_TX_END_TSTAMP     0x3cf4

#define CSR_NUM_PKT           0x3d00
#define CSR_PKT_GOOD          0x3d01
#define CSR_PKT_BAD           0x3d02
#define CSR_AVST_RX_ERR       0x3d07
#define CSR_RX_STA_TSTAMP     0x3d0b
#define CSR_RX_END_TSTAMP     0x3d0c

#define CSR_MAC_LOOP          0x3e00

#define ETHERNET_SPEED        10  // Gbps

#define USER_CLKFREQ_S10      156.25  // MHz
#define USER_CLKFREQ_AC       300.00  // MHz
#define BITSVER_MAJOR_S10     4
#define BITSVER_MAJOR_AC      5
#define DFL_BITSTREAM_ID      "bitstream_id"

#define FPGA_BBS_VER_MAJOR(i) (((i) >> 56) & 0xf)

class hssi_10g_cmd : public hssi_cmd
{
public:
  hssi_10g_cmd()
    : port_(0)
    , eth_loopback_("on")
    , he_loopback_("none")
    , num_packets_(1)
    , random_length_("fixed")
    , random_payload_("incremental")
    , packet_length_(64)
    , src_addr_("11:22:33:44:55:66")
    , dest_addr_("77:88:99:aa:bb:cc")
    , eth_ifc_("none")
    , rnd_seed0_(0x5eed0000)
    , rnd_seed1_(0x5eed0001)
    , rnd_seed2_(0x00025eed)
  {}

  virtual const char *name() const override
  {
    return "hssi_10g";
  }

  virtual const char *description() const override
  {
    return "hssi 10G test\n";
  }

  virtual void add_options(CLI::App *app) override
  {
    auto opt = app->add_option("--port", port_,
                               "QSFP port");
    opt->check(CLI::Range(0, 7))->default_str(std::to_string(port_));

    opt = app->add_option("--eth-loopback", eth_loopback_,
                    "whether to enable loopback on the eth interface");
    opt->check(CLI::IsMember({"on", "off"}))->default_str(eth_loopback_);

    opt = app->add_option("--he-loopback", he_loopback_,
                    "whether to enable loopback in the Hardware Exerciser (HE)");
    opt->check(CLI::IsMember({"on", "off"}))->default_str(he_loopback_);

    opt = app->add_option("--num-packets", num_packets_,
                          "number of packets");
    opt->default_str(std::to_string(num_packets_));

    opt = app->add_option("--random-length", random_length_,
                          "packet length randomization");
    opt->check(CLI::IsMember({"fixed", "random"}))->default_str(random_length_);

    opt = app->add_option("--random-payload", random_payload_,
                          "payload randomization");
    opt->check(CLI::IsMember({"incremental", "random"}))->default_str(random_payload_);

    opt = app->add_option("--packet-length", packet_length_,
                          "packet length");
    opt->default_str(std::to_string(packet_length_));

    opt = app->add_option("--src-addr", src_addr_,
                          "source MAC address");
    opt->default_str(src_addr_);

    opt = app->add_option("--dest-addr", dest_addr_,
                          "destination MAC address");
    opt->default_str(dest_addr_);

    opt = app->add_option("--eth-ifc", eth_ifc_,
                          "ethernet interface name");
    opt->default_str(eth_ifc_);

    opt = app->add_option("--rnd-seed0", rnd_seed0_,
                          "prbs generator [31:0]");
    opt->default_str(std::to_string(rnd_seed0_));

    opt = app->add_option("--rnd-seed1", rnd_seed1_,
                          "prbs generator [47:32]");
    opt->default_str(std::to_string(rnd_seed1_));

    opt = app->add_option("--rnd-seed2", rnd_seed2_,
                          "prbs generator [91:64]");
    opt->default_str(std::to_string(rnd_seed2_));
  }

  virtual int run(test_afu *afu, CLI::App *app) override
  {
    (void)app;

    hssi_afu *hafu = dynamic_cast<hssi_afu *>(afu);

    uint64_t bin_src_addr = mac_bits_for(src_addr_);
    if (bin_src_addr == INVALID_MAC) {
      std::cerr << "invalid MAC address: " << src_addr_ << std::endl;
      return test_afu::error;
    }

    uint64_t bin_dest_addr = mac_bits_for(dest_addr_);
    if (bin_dest_addr == INVALID_MAC) {
      std::cerr << "invalid MAC address: " << dest_addr_ << std::endl;
      return test_afu::error;
    }

    std::string eth_ifc = eth_ifc_;
    if (eth_ifc_ == "none")
        eth_ifc = hafu->ethernet_interface();

    std::cout << "10G loopback test" << std::endl
              << "  port: " << port_ << std::endl
              << "  eth_loopback: " << eth_loopback_ << std::endl
              << "  he_loopback: " << he_loopback_ << std::endl
              << "  num_packets: " << num_packets_ << std::endl
              << "  packet_length: " << packet_length_ << std::endl
              << "  src_address: " << src_addr_ << std::endl
              << "    (bits): 0x" << std::hex << bin_src_addr << std::endl
              << "  dest_address: " << dest_addr_ << std::endl
              << "    (bits): 0x" << std::hex << bin_dest_addr << std::endl
              << "  random_length: " << random_length_ << std::endl
              << "  random_payload: " << random_payload_ << std::endl
              << "  rnd_seed0: " << rnd_seed0_ << std::endl
              << "  rnd_seed1: " << rnd_seed1_ << std::endl
              << "  rnd_seed2: " << rnd_seed2_ << std::endl
              << "  eth: " << eth_ifc << std::endl
              << std::endl;

    if (eth_ifc == "") {
        std::cout << "No eth interface, so not "
                     "honoring --eth-loopback." << std::endl;
    } else {
        if (eth_loopback_ == "on")
            enable_eth_loopback(eth_ifc, true);
        else
            enable_eth_loopback(eth_ifc, false);
    }

    hafu->mbox_write(CSR_STOP, 0);

    hafu->write64(TRAFFIC_CTRL_PORT_SEL, port_);

    if (he_loopback_ != "none") {
        hafu->mbox_write(CSR_MAC_LOOP, (he_loopback_ == "on") ? 1 : 0);

        if (he_loopback_ != "on") // don't loop for "off"
            return test_afu::success;

        std::cout << "HE loopback enabled. Use Ctrl+C to exit." << std::endl;

        while (running_) {
            std::this_thread::sleep_for(std::chrono::milliseconds(1000));
        }

        return test_afu::success;
    }

    hafu->mbox_write(CSR_NUM_PACKETS, num_packets_);

    hafu->mbox_write(CSR_PACKET_LENGTH, packet_length_);

    hafu->mbox_write(CSR_SRC_ADDR0, static_cast<uint32_t>(bin_src_addr));
    hafu->mbox_write(CSR_SRC_ADDR1, static_cast<uint32_t>(bin_src_addr >> 32));

    hafu->mbox_write(CSR_DEST_ADDR0, static_cast<uint32_t>(bin_dest_addr));
    hafu->mbox_write(CSR_DEST_ADDR1, static_cast<uint32_t>(bin_dest_addr >> 32));

    hafu->mbox_write(CSR_RANDOM_LENGTH, (random_length_ == "fixed") ? 0 : 1);
    hafu->mbox_write(CSR_RANDOM_PAYLOAD, (random_payload_ == "incremental") ? 0 : 1);
    hafu->mbox_write(CSR_RND_SEED0, rnd_seed0_);
    hafu->mbox_write(CSR_RND_SEED1, rnd_seed1_);
    hafu->mbox_write(CSR_RND_SEED2, rnd_seed2_);

    hafu->mbox_write(CSR_START, 1);

    print_registers(std::cout, hafu);

    uint32_t count;
    const uint64_t interval = 100ULL;
    do
    {
      count = hafu->mbox_read(CSR_PACKET_TX_COUNT);
  
      if (!running_) {
        hafu->mbox_write(CSR_STOP, 1);
        return test_afu::error;
      }
  
      std::this_thread::sleep_for(std::chrono::microseconds(interval));
    } while(count < num_packets_);

    std::cout << std::endl;

    hssi_perf(hafu);

    if (eth_ifc == "") {
        std::cout << "No eth interface, so not "
                     "showing stats." << std::endl;
    } else {
        show_eth_stats(eth_ifc);

        if (eth_loopback_ == "on")
            enable_eth_loopback(eth_ifc, false);
    }

    return test_afu::success;
  }

  void hssi_perf(hssi_afu *hafu)
  {
    fpga_properties pprops = NULL;
    fpga_result res = FPGA_OK;
    uint32_t num_matches = 1;
    uint64_t bitstream_id;
    double clk_freq = 0;    
    uint32_t major = 0;
    fpga_token token;  

    std::cout << "HSSI performance: " << std::endl;

    res = fpgaGetProperties(NULL, &pprops);
    if (res != FPGA_OK) {
            std::cerr << "Failed to get properties" << std::endl;
            return;
    }

    res = fpgaPropertiesSetObjectType(pprops, FPGA_DEVICE);
    if (res != FPGA_OK) {
            std::cerr << "Failed to set type to FPGA_DEVICE" << std::endl;
            return;
    }

    fpgaEnumerate(&pprops, 1, &token, 1, &num_matches);

    if (0 != num_matches) {
            // Retrieve the Bitstream ID 
            fpgaDestroyProperties(&pprops);
            fpgaGetProperties(token, &pprops);
            res = fpgaPropertiesGetBBSID(pprops, &bitstream_id);
            if (res != FPGA_OK) {
                    std::cerr << "Failed to read bitstream id from properties" << std::endl;
                    return;
            }

        major = FPGA_BBS_VER_MAJOR(bitstream_id);
        if (major == BITSVER_MAJOR_S10)
            clk_freq = USER_CLKFREQ_S10;
        else if (major == BITSVER_MAJOR_AC)
            clk_freq = USER_CLKFREQ_AC;
        else {
                fpgaDestroyToken(&token);
                fpgaDestroyProperties(&pprops);
                std::cout << "unknown platform" << std::endl;
                return;
        }

            fpgaDestroyToken(&token);
    }
    else
    {
            std::cerr << "No FPGA found" << std::endl;
        fpgaDestroyProperties(&pprops);
        return;
    }

    fpgaDestroyProperties(&pprops);

    // Reading traffic control Tx/Rx timestamp registers 
    uint32_t tx_end_tstamp = hafu->mbox_read(CSR_TX_END_TSTAMP);
    uint32_t rx_sta_tstamp = hafu->mbox_read(CSR_RX_STA_TSTAMP);
    uint32_t rx_end_tstamp = hafu->mbox_read(CSR_RX_END_TSTAMP);

    // Convert timestamp register from clock cycles to nanosecond
    double sample_period_ns = 1000 / clk_freq;
    double tx_end_tstamp_ns = tx_end_tstamp * sample_period_ns;
    double rx_sta_tstamp_ns = rx_sta_tstamp * sample_period_ns;
    double rx_end_tstamp_ns = rx_end_tstamp * sample_period_ns;
    
    // Calculate latencies
    double latency_min_ns = rx_sta_tstamp_ns; 
    double latency_max_ns = rx_end_tstamp_ns - tx_end_tstamp_ns;

    // Calculate Tx/Rx throughput achieved
    uint32_t data_pkt_size = packet_length_ - 4;
    double total_tx_duration_ns = tx_end_tstamp_ns;
    double total_rx_duration_ns = (rx_end_tstamp_ns - rx_sta_tstamp_ns);
    uint32_t total_data_size_bits = (num_packets_  * data_pkt_size * 8) ;
    double achieved_tx_tput_gbps = (total_data_size_bits / total_tx_duration_ns);
    double achieved_rx_tput_gbps = (total_data_size_bits / total_rx_duration_ns);

    std::cout << "\tSelected clock frequency : "<< clk_freq << " MHz" << std::endl
                  << "\tLatency minimum : " << latency_min_ns <<" ns"<<std::endl
                  << "\tLatency maximum : " << latency_max_ns <<" ns"<<std::endl
                  << "\tAchieved Tx throughput : " << achieved_tx_tput_gbps << " GB/s" << std::endl
                  << "\tAchieved Rx throughput : " << achieved_rx_tput_gbps << " GB/s" << std::endl
                  << std::endl;
  }

  virtual const char *afu_id() const override
  {
    return "823c334c-98bf-11ea-bb37-0242ac130002";
  }

  std::ostream & print_registers(std::ostream &os, hssi_afu *hafu) const
  {
    os << "0x40000 " << std::setw(21) << "ETH_AFU_DFH" << ": " <<
      int_to_hex(hafu->read64(ETH_AFU_DFH)) << std::endl;
    os << "0x40008 " << std::setw(21) << "ETH_AFU_ID_L" << ": " <<
      int_to_hex(hafu->read64(ETH_AFU_ID_L)) << std::endl;
    os << "0x40010 " << std::setw(21) << "ETH_AFU_ID_H" << ": " <<
      int_to_hex(hafu->read64(ETH_AFU_ID_H)) << std::endl;
    os << "0x40030 " << std::setw(21) << "TRAFFIC_CTRL_CMD" << ": " <<
      int_to_hex(hafu->read64(TRAFFIC_CTRL_CMD)) << std::endl;
    os << "0x40038 " << std::setw(21) << "TRAFFIC_CTRL_DATA" << ": " <<
      int_to_hex(hafu->read64(TRAFFIC_CTRL_DATA)) << std::endl;
    os << "0x40040 " << std::setw(21) << "TRAFFIC_CTRL_PORT_SEL" << ": " <<
      int_to_hex(hafu->read64(TRAFFIC_CTRL_PORT_SEL)) << std::endl;
    os << "0x40048 " << std::setw(21) << "AFU_SCRATCHPAD" << ": " <<
      int_to_hex(hafu->read64(AFU_SCRATCHPAD)) << std::endl;
    
    os << std::endl;

    os << "0x3c00 " << std::setw(22) << "number_packets" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_NUM_PACKETS)) << std::endl;
    os << "0x3c01 " << std::setw(22) << "random_length" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_RANDOM_LENGTH)) << std::endl;
    os << "0x3c02 " << std::setw(22) << "random_payload" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_RANDOM_PAYLOAD)) << std::endl;
    os << "0x3c03 " << std::setw(22) << "start" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_START)) << std::endl;
    os << "0x3c04 " << std::setw(22) << "stop" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_STOP)) << std::endl;
    os << "0x3c05 " << std::setw(22) << "source_addr0" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_SRC_ADDR0)) << std::endl;
    os << "0x3c06 " << std::setw(22) << "source_addr1" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_SRC_ADDR1)) << std::endl;
    os << "0x3c07 " << std::setw(22) << "dest_addr0" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_DEST_ADDR0)) << std::endl;
    os << "0x3c08 " << std::setw(22) << "dest_addr1" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_DEST_ADDR1)) << std::endl;
    os << "0x3c09 " << std::setw(22) << "packet_tx_count" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_PACKET_TX_COUNT)) << std::endl;
    os << "0x3c0a " << std::setw(22) << "rnd_seed0" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_RND_SEED0)) << std::endl;
    os << "0x3c0b " << std::setw(22) << "rnd_seed1" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_RND_SEED1)) << std::endl;
    os << "0x3c0c " << std::setw(22) << "rnd_seed2" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_RND_SEED2)) << std::endl;
    os << "0x3c0d " << std::setw(22) << "pkt_length" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_PACKET_LENGTH)) << std::endl;
  
    os << "0x3d00 " << std::setw(22) << "num_pkt" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_NUM_PKT)) << std::endl;
    os << "0x3d01 " << std::setw(22) << "pkt_good" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_PKT_GOOD)) << std::endl;
    os << "0x3d02 " << std::setw(22) << "pkt_bad" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_PKT_BAD)) << std::endl;
    os << "0x3d07 " << std::setw(22) << "avst_rx_err" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_AVST_RX_ERR)) << std::endl;
  
    os << "0x3e00 " << std::setw(22) << "mac_loop" << ": " <<
      int_to_hex(hafu->mbox_read(CSR_MAC_LOOP)) << std::endl;

    return os;
  }

protected:
  uint32_t port_;
  std::string eth_loopback_;
  std::string he_loopback_;
  uint32_t num_packets_;
  std::string random_length_;
  std::string random_payload_;
  uint32_t packet_length_;
  std::string src_addr_;
  std::string dest_addr_;
  std::string eth_ifc_;
  uint32_t rnd_seed0_;
  uint32_t rnd_seed1_;
  uint32_t rnd_seed2_;
};

1	// Copyright(c) 2020-2021, Intel Corporation
2	//
3	// Redistribution and use in source and binary forms, with or without
4	// modification, are permitted provided that the following conditions are met:
5	//
6	// * Redistributions of source code must retain the above copyright notice,
7	// this list of conditions and the following disclaimer.
8	// * Redistributions in binary form must reproduce the above copyright notice,
9	// this list of conditions and the following disclaimer in the documentation
10	// and/or other materials provided with the distribution.
11	// * Neither the name of Intel Corporation nor the names of its contributors
12	// may be used to endorse or promote products derived from this software
13	// without specific prior written permission.
14	//
15	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16	// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19	// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20	// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21	// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22	// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23	// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24	// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25	// POSSIBILITY OF SUCH DAMAGE.
26	#pragma once
27	#include <iostream>
28	#include <string>
29	#include "hssi_cmd.h"
30
31	#define CSR_NUM_PACKETS 0x3c00
32	#define CSR_RANDOM_LENGTH 0x3c01
33	#define CSR_RANDOM_PAYLOAD 0x3c02
34	#define CSR_START 0x3c03
35	#define CSR_STOP 0x3c04
36	#define CSR_SRC_ADDR0 0x3c05
37	#define CSR_SRC_ADDR1 0x3c06
38	#define CSR_DEST_ADDR0 0x3c07
39	#define CSR_DEST_ADDR1 0x3c08
40	#define CSR_PACKET_TX_COUNT 0x3c09
41	#define CSR_RND_SEED0 0x3c0a
42	#define CSR_RND_SEED1 0x3c0b
43	#define CSR_RND_SEED2 0x3c0c
44	#define CSR_PACKET_LENGTH 0x3c0d
45	#define CSR_TX_END_TSTAMP 0x3cf4
46
47	#define CSR_NUM_PKT 0x3d00
48	#define CSR_PKT_GOOD 0x3d01
49	#define CSR_PKT_BAD 0x3d02
50	#define CSR_AVST_RX_ERR 0x3d07
51	#define CSR_RX_STA_TSTAMP 0x3d0b
52	#define CSR_RX_END_TSTAMP 0x3d0c
53
54	#define CSR_MAC_LOOP 0x3e00
55
56	#define ETHERNET_SPEED 10 // Gbps
57
58	#define USER_CLKFREQ_S10 156.25 // MHz
59	#define USER_CLKFREQ_AC 300.00 // MHz
60	#define BITSVER_MAJOR_S10 4
61	#define BITSVER_MAJOR_AC 5
62	#define DFL_BITSTREAM_ID "bitstream_id"
63
64	#define FPGA_BBS_VER_MAJOR(i) (((i) >> 56) & 0xf)
65
66	class hssi_10g_cmd : public hssi_cmd
67	{
68	public:
69	hssi_10g_cmd()	×
70	: port_(0)	×
71	, eth_loopback_("on")
72	, he_loopback_("none")
73	, num_packets_(1)
74	, random_length_("fixed")
75	, random_payload_("incremental")
76	, packet_length_(64)
77	, src_addr_("11:22:33:44:55:66")
78	, dest_addr_("77:88:99:aa:bb:cc")
79	, eth_ifc_("none")
80	, rnd_seed0_(0x5eed0000)
81	, rnd_seed1_(0x5eed0001)
82	, rnd_seed2_(0x00025eed)	×
83	{}	×
84
85	virtual const char *name() const override	×
86	{
87	return "hssi_10g";	×
88	}
89
90	virtual const char *description() const override	×
91	{
92	return "hssi 10G test\n";	×
93	}
94
95	virtual void add_options(CLI::App *app) override	×
96	{
97	auto opt = app->add_option("--port", port_,	×
98	"QSFP port");
99	opt->check(CLI::Range(0, 7))->default_str(std::to_string(port_));	×
100
101	opt = app->add_option("--eth-loopback", eth_loopback_,	×
102	"whether to enable loopback on the eth interface");
103	opt->check(CLI::IsMember({"on", "off"}))->default_str(eth_loopback_);	×
104
105	opt = app->add_option("--he-loopback", he_loopback_,	×
106	"whether to enable loopback in the Hardware Exerciser (HE)");
107	opt->check(CLI::IsMember({"on", "off"}))->default_str(he_loopback_);	×
108
109	opt = app->add_option("--num-packets", num_packets_,	×
110	"number of packets");
111	opt->default_str(std::to_string(num_packets_));	×
112
113	opt = app->add_option("--random-length", random_length_,	×
114	"packet length randomization");
115	opt->check(CLI::IsMember({"fixed", "random"}))->default_str(random_length_);	×
116
117	opt = app->add_option("--random-payload", random_payload_,	×
118	"payload randomization");
119	opt->check(CLI::IsMember({"incremental", "random"}))->default_str(random_payload_);	×
120
121	opt = app->add_option("--packet-length", packet_length_,	×
122	"packet length");
123	opt->default_str(std::to_string(packet_length_));	×
124
125	opt = app->add_option("--src-addr", src_addr_,	×
126	"source MAC address");
127	opt->default_str(src_addr_);	×
128
129	opt = app->add_option("--dest-addr", dest_addr_,	×
130	"destination MAC address");
131	opt->default_str(dest_addr_);	×
132
133	opt = app->add_option("--eth-ifc", eth_ifc_,	×
134	"ethernet interface name");
135	opt->default_str(eth_ifc_);	×
136
137	opt = app->add_option("--rnd-seed0", rnd_seed0_,	×
138	"prbs generator [31:0]");
139	opt->default_str(std::to_string(rnd_seed0_));	×
140
141	opt = app->add_option("--rnd-seed1", rnd_seed1_,	×
142	"prbs generator [47:32]");
143	opt->default_str(std::to_string(rnd_seed1_));	×
144
145	opt = app->add_option("--rnd-seed2", rnd_seed2_,	×
146	"prbs generator [91:64]");
147	opt->default_str(std::to_string(rnd_seed2_));	×
148	}	×
149
150	virtual int run(test_afu afu, CLI::App app) override	×
151	{
152	(void)app;
153
154	hssi_afu hafu = dynamic_cast<hssi_afu >(afu);	×
155
156	uint64_t bin_src_addr = mac_bits_for(src_addr_);	×
157	if (bin_src_addr == INVALID_MAC) {	×
158	std::cerr << "invalid MAC address: " << src_addr_ << std::endl;	×
159	return test_afu::error;	×
160	}
161
162	uint64_t bin_dest_addr = mac_bits_for(dest_addr_);	×
163	if (bin_dest_addr == INVALID_MAC) {	×
164	std::cerr << "invalid MAC address: " << dest_addr_ << std::endl;	×
165	return test_afu::error;	×
166	}
167
168	std::string eth_ifc = eth_ifc_;	×
169	if (eth_ifc_ == "none")	×
170	eth_ifc = hafu->ethernet_interface();	×
171
172	std::cout << "10G loopback test" << std::endl	×
173	<< " port: " << port_ << std::endl	×
174	<< " eth_loopback: " << eth_loopback_ << std::endl	×
175	<< " he_loopback: " << he_loopback_ << std::endl	×
176	<< " num_packets: " << num_packets_ << std::endl	×
177	<< " packet_length: " << packet_length_ << std::endl	×
178	<< " src_address: " << src_addr_ << std::endl	×
179	<< " (bits): 0x" << std::hex << bin_src_addr << std::endl	×
180	<< " dest_address: " << dest_addr_ << std::endl	×
181	<< " (bits): 0x" << std::hex << bin_dest_addr << std::endl	×
182	<< " random_length: " << random_length_ << std::endl	×
183	<< " random_payload: " << random_payload_ << std::endl	×
184	<< " rnd_seed0: " << rnd_seed0_ << std::endl	×
185	<< " rnd_seed1: " << rnd_seed1_ << std::endl	×
186	<< " rnd_seed2: " << rnd_seed2_ << std::endl	×
187	<< " eth: " << eth_ifc << std::endl	×
188	<< std::endl;	×
189
190	if (eth_ifc == "") {	×
191	std::cout << "No eth interface, so not "
192	"honoring --eth-loopback." << std::endl;	×
193	} else {
194	if (eth_loopback_ == "on")	×
195	enable_eth_loopback(eth_ifc, true);	×
196	else
197	enable_eth_loopback(eth_ifc, false);	×
198	}
199
200	hafu->mbox_write(CSR_STOP, 0);	×
201
202	hafu->write64(TRAFFIC_CTRL_PORT_SEL, port_);	×
203
204	if (he_loopback_ != "none") {	×
205	hafu->mbox_write(CSR_MAC_LOOP, (he_loopback_ == "on") ? 1 : 0);	×
206
207	if (he_loopback_ != "on") // don't loop for "off"	×
208	return test_afu::success;	×
209
210	std::cout << "HE loopback enabled. Use Ctrl+C to exit." << std::endl;	×
211
212	while (running_) {	×
213	std::this_thread::sleep_for(std::chrono::milliseconds(1000));	×
214	}
215
216	return test_afu::success;	×
217	}
218
219	hafu->mbox_write(CSR_NUM_PACKETS, num_packets_);	×
220
221	hafu->mbox_write(CSR_PACKET_LENGTH, packet_length_);	×
222
223	hafu->mbox_write(CSR_SRC_ADDR0, static_cast<uint32_t>(bin_src_addr));	×
224	hafu->mbox_write(CSR_SRC_ADDR1, static_cast<uint32_t>(bin_src_addr >> 32));	×
225
226	hafu->mbox_write(CSR_DEST_ADDR0, static_cast<uint32_t>(bin_dest_addr));	×
227	hafu->mbox_write(CSR_DEST_ADDR1, static_cast<uint32_t>(bin_dest_addr >> 32));	×
228
229	hafu->mbox_write(CSR_RANDOM_LENGTH, (random_length_ == "fixed") ? 0 : 1);	×
230	hafu->mbox_write(CSR_RANDOM_PAYLOAD, (random_payload_ == "incremental") ? 0 : 1);	×
231	hafu->mbox_write(CSR_RND_SEED0, rnd_seed0_);	×
232	hafu->mbox_write(CSR_RND_SEED1, rnd_seed1_);	×
233	hafu->mbox_write(CSR_RND_SEED2, rnd_seed2_);	×
234
235	hafu->mbox_write(CSR_START, 1);	×
236
237	print_registers(std::cout, hafu);	×
238
239	uint32_t count;
240	const uint64_t interval = 100ULL;	×
241	do	×
242	{
243	count = hafu->mbox_read(CSR_PACKET_TX_COUNT);	×
244
245	if (!running_) {	×
246	hafu->mbox_write(CSR_STOP, 1);	×
247	return test_afu::error;	×
248	}
249
250	std::this_thread::sleep_for(std::chrono::microseconds(interval));	×
251	} while(count < num_packets_);	×
252
253	std::cout << std::endl;	×
254
255	hssi_perf(hafu);	×
256
257	if (eth_ifc == "") {	×
258	std::cout << "No eth interface, so not "
259	"showing stats." << std::endl;	×
260	} else {
261	show_eth_stats(eth_ifc);	×
262
263	if (eth_loopback_ == "on")	×
264	enable_eth_loopback(eth_ifc, false);	×
265	}
266
267	return test_afu::success;	×
268	}
269
270	void hssi_perf(hssi_afu *hafu)	×
271	{
272	fpga_properties pprops = NULL;	×
273	fpga_result res = FPGA_OK;	×
274	uint32_t num_matches = 1;	×
275	uint64_t bitstream_id;
276	double clk_freq = 0;	×
277	uint32_t major = 0;	×
278	fpga_token token;
279
280	std::cout << "HSSI performance: " << std::endl;	×
281
282	res = fpgaGetProperties(NULL, &pprops);	×
283	if (res != FPGA_OK) {	×
284	std::cerr << "Failed to get properties" << std::endl;	×
285	return;	×
286	}
287
288	res = fpgaPropertiesSetObjectType(pprops, FPGA_DEVICE);	×
289	if (res != FPGA_OK) {	×
290	std::cerr << "Failed to set type to FPGA_DEVICE" << std::endl;	×
291	return;	×
292	}
293
294	fpgaEnumerate(&pprops, 1, &token, 1, &num_matches);	×
295
296	if (0 != num_matches) {	×
297	// Retrieve the Bitstream ID
298	fpgaDestroyProperties(&pprops);	×
299	fpgaGetProperties(token, &pprops);	×
300	res = fpgaPropertiesGetBBSID(pprops, &bitstream_id);	×
301	if (res != FPGA_OK) {	×
302	std::cerr << "Failed to read bitstream id from properties" << std::endl;	×
303	return;	×
304	}
305
306	major = FPGA_BBS_VER_MAJOR(bitstream_id);	×
307	if (major == BITSVER_MAJOR_S10)	×
308	clk_freq = USER_CLKFREQ_S10;	×
309	else if (major == BITSVER_MAJOR_AC)	×
310	clk_freq = USER_CLKFREQ_AC;	×
311	else {
312	fpgaDestroyToken(&token);	×
313	fpgaDestroyProperties(&pprops);	×
314	std::cout << "unknown platform" << std::endl;	×
315	return;	×
316	}
317
318	fpgaDestroyToken(&token);	×
319	}
320	else
321	{
322	std::cerr << "No FPGA found" << std::endl;	×
323	fpgaDestroyProperties(&pprops);	×
324	return;	×
325	}
326
327	fpgaDestroyProperties(&pprops);	×
328
329	// Reading traffic control Tx/Rx timestamp registers
330	uint32_t tx_end_tstamp = hafu->mbox_read(CSR_TX_END_TSTAMP);	×
331	uint32_t rx_sta_tstamp = hafu->mbox_read(CSR_RX_STA_TSTAMP);	×
332	uint32_t rx_end_tstamp = hafu->mbox_read(CSR_RX_END_TSTAMP);	×
333
334	// Convert timestamp register from clock cycles to nanosecond
335	double sample_period_ns = 1000 / clk_freq;	×
336	double tx_end_tstamp_ns = tx_end_tstamp * sample_period_ns;	×
337	double rx_sta_tstamp_ns = rx_sta_tstamp * sample_period_ns;	×
338	double rx_end_tstamp_ns = rx_end_tstamp * sample_period_ns;	×
339
340	// Calculate latencies
341	double latency_min_ns = rx_sta_tstamp_ns;	×
342	double latency_max_ns = rx_end_tstamp_ns - tx_end_tstamp_ns;	×
343
344	// Calculate Tx/Rx throughput achieved
345	uint32_t data_pkt_size = packet_length_ - 4;	×
346	double total_tx_duration_ns = tx_end_tstamp_ns;	×
347	double total_rx_duration_ns = (rx_end_tstamp_ns - rx_sta_tstamp_ns);	×
348	uint32_t total_data_size_bits = (num_packets_ * data_pkt_size * 8) ;	×
349	double achieved_tx_tput_gbps = (total_data_size_bits / total_tx_duration_ns);	×
350	double achieved_rx_tput_gbps = (total_data_size_bits / total_rx_duration_ns);	×
351
352	std::cout << "\tSelected clock frequency : "<< clk_freq << " MHz" << std::endl	×
353	<< "\tLatency minimum : " << latency_min_ns <<" ns"<<std::endl	×
354	<< "\tLatency maximum : " << latency_max_ns <<" ns"<<std::endl	×
355	<< "\tAchieved Tx throughput : " << achieved_tx_tput_gbps << " GB/s" << std::endl	×
356	<< "\tAchieved Rx throughput : " << achieved_rx_tput_gbps << " GB/s" << std::endl	×
357	<< std::endl;	×
358	}
359
360	virtual const char *afu_id() const override	×
361	{
362	return "823c334c-98bf-11ea-bb37-0242ac130002";	×
363	}
364
365	std::ostream & print_registers(std::ostream &os, hssi_afu *hafu) const	×
366	{
367	os << "0x40000 " << std::setw(21) << "ETH_AFU_DFH" << ": " <<
368	int_to_hex(hafu->read64(ETH_AFU_DFH)) << std::endl;	×
369	os << "0x40008 " << std::setw(21) << "ETH_AFU_ID_L" << ": " <<
370	int_to_hex(hafu->read64(ETH_AFU_ID_L)) << std::endl;	×
371	os << "0x40010 " << std::setw(21) << "ETH_AFU_ID_H" << ": " <<
372	int_to_hex(hafu->read64(ETH_AFU_ID_H)) << std::endl;	×
373	os << "0x40030 " << std::setw(21) << "TRAFFIC_CTRL_CMD" << ": " <<
374	int_to_hex(hafu->read64(TRAFFIC_CTRL_CMD)) << std::endl;	×
375	os << "0x40038 " << std::setw(21) << "TRAFFIC_CTRL_DATA" << ": " <<
376	int_to_hex(hafu->read64(TRAFFIC_CTRL_DATA)) << std::endl;	×
377	os << "0x40040 " << std::setw(21) << "TRAFFIC_CTRL_PORT_SEL" << ": " <<
378	int_to_hex(hafu->read64(TRAFFIC_CTRL_PORT_SEL)) << std::endl;	×
379	os << "0x40048 " << std::setw(21) << "AFU_SCRATCHPAD" << ": " <<
380	int_to_hex(hafu->read64(AFU_SCRATCHPAD)) << std::endl;	×
381
382	os << std::endl;	×
383
384	os << "0x3c00 " << std::setw(22) << "number_packets" << ": " <<
385	int_to_hex(hafu->mbox_read(CSR_NUM_PACKETS)) << std::endl;	×
386	os << "0x3c01 " << std::setw(22) << "random_length" << ": " <<
387	int_to_hex(hafu->mbox_read(CSR_RANDOM_LENGTH)) << std::endl;	×
388	os << "0x3c02 " << std::setw(22) << "random_payload" << ": " <<
389	int_to_hex(hafu->mbox_read(CSR_RANDOM_PAYLOAD)) << std::endl;	×
390	os << "0x3c03 " << std::setw(22) << "start" << ": " <<
391	int_to_hex(hafu->mbox_read(CSR_START)) << std::endl;	×
392	os << "0x3c04 " << std::setw(22) << "stop" << ": " <<
393	int_to_hex(hafu->mbox_read(CSR_STOP)) << std::endl;	×
394	os << "0x3c05 " << std::setw(22) << "source_addr0" << ": " <<
395	int_to_hex(hafu->mbox_read(CSR_SRC_ADDR0)) << std::endl;	×
396	os << "0x3c06 " << std::setw(22) << "source_addr1" << ": " <<
397	int_to_hex(hafu->mbox_read(CSR_SRC_ADDR1)) << std::endl;	×
398	os << "0x3c07 " << std::setw(22) << "dest_addr0" << ": " <<
399	int_to_hex(hafu->mbox_read(CSR_DEST_ADDR0)) << std::endl;	×
400	os << "0x3c08 " << std::setw(22) << "dest_addr1" << ": " <<
401	int_to_hex(hafu->mbox_read(CSR_DEST_ADDR1)) << std::endl;	×
402	os << "0x3c09 " << std::setw(22) << "packet_tx_count" << ": " <<
403	int_to_hex(hafu->mbox_read(CSR_PACKET_TX_COUNT)) << std::endl;	×
404	os << "0x3c0a " << std::setw(22) << "rnd_seed0" << ": " <<
405	int_to_hex(hafu->mbox_read(CSR_RND_SEED0)) << std::endl;	×
406	os << "0x3c0b " << std::setw(22) << "rnd_seed1" << ": " <<
407	int_to_hex(hafu->mbox_read(CSR_RND_SEED1)) << std::endl;	×
408	os << "0x3c0c " << std::setw(22) << "rnd_seed2" << ": " <<
409	int_to_hex(hafu->mbox_read(CSR_RND_SEED2)) << std::endl;	×
410	os << "0x3c0d " << std::setw(22) << "pkt_length" << ": " <<
411	int_to_hex(hafu->mbox_read(CSR_PACKET_LENGTH)) << std::endl;	×
412
413	os << "0x3d00 " << std::setw(22) << "num_pkt" << ": " <<
414	int_to_hex(hafu->mbox_read(CSR_NUM_PKT)) << std::endl;	×
415	os << "0x3d01 " << std::setw(22) << "pkt_good" << ": " <<
416	int_to_hex(hafu->mbox_read(CSR_PKT_GOOD)) << std::endl;	×
417	os << "0x3d02 " << std::setw(22) << "pkt_bad" << ": " <<
418	int_to_hex(hafu->mbox_read(CSR_PKT_BAD)) << std::endl;	×
419	os << "0x3d07 " << std::setw(22) << "avst_rx_err" << ": " <<
420	int_to_hex(hafu->mbox_read(CSR_AVST_RX_ERR)) << std::endl;	×
421
422	os << "0x3e00 " << std::setw(22) << "mac_loop" << ": " <<
423	int_to_hex(hafu->mbox_read(CSR_MAC_LOOP)) << std::endl;	×
424
425	return os;	×
426	}
427
428	protected:
429	uint32_t port_;
430	std::string eth_loopback_;
431	std::string he_loopback_;
432	uint32_t num_packets_;
433	std::string random_length_;
434	std::string random_payload_;
435	uint32_t packet_length_;
436	std::string src_addr_;
437	std::string dest_addr_;
438	std::string eth_ifc_;
439	uint32_t rnd_seed0_;
440	uint32_t rnd_seed1_;
441	uint32_t rnd_seed2_;
442	};

OPAE / opae-sdk / 1564305599

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