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0.0

/samples/fpgaperf_counter/fpgaperf_counter.c

// Copyright(c) 2021, Intel Corporation
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.

#include "fpgaperf_counter.h"

#include <errno.h>
#include <glob.h>
#include <regex.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <unistd.h>
#include <sys/ioctl.h>
#include <sys/syscall.h>
#include <libudev.h>
#include <linux/perf_event.h>

#include <opae/fpga.h>
#include <opae/log.h>
#include <opae/properties.h>
#include <opae/utils.h>
#include "opae_int.h"

#define PCI_DEV_ADDRS                "/sys/bus/pci/devices/*%x*:*%x*:*%x*.*%x*/"

#define DFL_PERF_FME                PCI_DEV_ADDRS "fpga_region/region*/dfl-fme.*"

#define DFL_PERF_SYSFS                "/sys/bus/event_source/devices/dfl_fme"

#define PERF_EVENT                "event=(0x[0-9a-fA-F]{2}),"

#define PERF_EVTYPE                "evtype=(0x[0-9a-fA-F]{2}),"

#define PERF_PORTID                "portid=(0x[0-9a-fA-F]{2})"

#define PERF_EVENT_PATTERN        PERF_EVENT PERF_EVTYPE PERF_PORTID

#define PERF_CONFIG_PATTERN        "config:([0-9]{1,})-([0-9]{2,})"

#define PARSE_MATCH_INT(_p, _m, _v, _b)                                \
        do {                                                        \
                errno = 0;                                        \
                _v = strtoul(_p + _m, NULL, _b);                \
                if (errno) {                                        \
                        OPAE_MSG("error parsing int");                \
                }                                                \
        } while (0)


/* Read format structure*/
struct read_format {
        uint64_t nr;
        struct {
                uint64_t value;
                uint64_t id;
        } values[];
};

/*
 * Check perf handle object for validity and lock its mutex
 * If fpga_perf_check_and_lock() returns FPGA_OK, assume the mutex to be
 * locked.
 */
STATIC fpga_result fpga_perf_check_and_lock(fpga_perf_counter *fpga_perf)
{
        int res = 0;

        if (!fpga_perf)
                return FPGA_INVALID_PARAM;

        if (opae_mutex_lock(res, &fpga_perf->lock)) {
                OPAE_ERR("Failed to lock perf mutex");
                return FPGA_EXCEPTION;
        }

        if (fpga_perf->magic != FPGA_PERF_MAGIC) {
                opae_mutex_unlock(res, &fpga_perf->lock);
                return FPGA_INVALID_PARAM;
        }

        return FPGA_OK;
}

/* parse the each format and get the shift val
 * parse the events for the particular device directory */
STATIC fpga_result parse_perf_attributes(struct udev_device *dev,
                        fpga_perf_counter *fpga_perf, const char *attr)
{
        regex_t re;
        char err[128]                                 = { 0 };
        int reg_res                                 = 0;
        uint64_t loop                                 = 0;
        uint64_t inner_loop                        = 0;
        uint64_t value                                 = 0;
        char attr_path[DFL_PERF_STR_MAX]        = { 0,};
        char attr_value[128]                        = { 0,};
        int  gres                                = 0;
        size_t i                                = 0;
        FILE *file                                = NULL;
        glob_t pglob;
        regmatch_t f_matches[3]                        = { {0} };
        regmatch_t e_matches[4]                        = { {0} };

        if (!dev || !fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }

        if (snprintf(attr_path, sizeof(attr_path), "%s/%s/*",
                        udev_device_get_syspath(dev), attr) < 0) {
                OPAE_ERR("snprintf buffer overflow");
                return FPGA_EXCEPTION;
        }
        gres = glob(attr_path, GLOB_NOSORT, NULL, &pglob);
        if (gres || !pglob.gl_pathc) {
                OPAE_ERR("Failed pattern match %s", attr_path);
                globfree(&pglob);
                return FPGA_EXCEPTION;
        }
        if (strcmp(attr, "format") == 0 ) {
                fpga_perf->num_format = pglob.gl_pathc;
                if (!fpga_perf->format_type) {
                        fpga_perf->format_type = calloc(fpga_perf->num_format,
                                                sizeof(perf_format_type));
                        if (!fpga_perf->format_type) {
                                fpga_perf->num_format = 0;
                                OPAE_ERR("Failed to allocate Memory");
                                globfree(&pglob);
                                return FPGA_NO_MEMORY;
                        }
                }
        } else {
                fpga_perf->num_perf_events = pglob.gl_pathc;
                if (!fpga_perf->perf_events) {
                        fpga_perf->perf_events = calloc(fpga_perf->num_perf_events,
                                                        sizeof(perf_events_type));
                        if (!fpga_perf->perf_events) {
                                fpga_perf->num_perf_events = 0;
                                OPAE_ERR("Failed to allocate Memory");
                                globfree(&pglob);
                                return FPGA_NO_MEMORY;
                        }
                }
        }

        for (i = 0; i < pglob.gl_pathc; i++) {
                file = fopen(pglob.gl_pathv[i], "r");
                if (!file) {
                        OPAE_ERR("fopen(%s) failed\n", pglob.gl_pathv[i]);
                        globfree(&pglob);
                        return FPGA_EXCEPTION;
                }
                if (fscanf(file, "%127s", attr_value) != 1) {
                        OPAE_ERR("Failed to read %s", pglob.gl_pathv[i]);
                        goto out;
                }
                if (strcmp(attr, "format") == 0 ) {
                        reg_res = regcomp(&re, PERF_CONFIG_PATTERN,
                                REG_EXTENDED | REG_ICASE);
                        if (reg_res) {
                                OPAE_ERR("Error compiling regex");
                                goto out;
                        }
                        reg_res = regexec(&re, attr_value, 4, f_matches, 0);
                        if (reg_res) {
                                regerror(reg_res, &re, err, sizeof(err));
                                OPAE_MSG("Error executing regex: %s", err);
                        } else {
                                PARSE_MATCH_INT(attr_value, f_matches[1].rm_so, value, 10);
                                fpga_perf->format_type[loop].shift = value;
                                if (snprintf(fpga_perf->format_type[loop].format_name,
                                        sizeof(fpga_perf->format_type[loop].format_name),
                                                "%s", (strstr(pglob.gl_pathv[i], attr)
                                                        + strlen(attr)+1)) < 0) {
                                        OPAE_ERR("snprintf buffer overflow");
                                        goto out;
                                }
                                loop++;
                        }
                } else {
                        reg_res = regcomp(&re, PERF_EVENT_PATTERN,
                                REG_EXTENDED | REG_ICASE);
                        if (reg_res) {
                                OPAE_ERR("Error compiling regex");
                                goto out;
                        }
                        reg_res = regexec(&re, attr_value, 4, e_matches, 0);
                        if (reg_res) {
                                regerror(reg_res, &re, err, sizeof(err));
                                OPAE_MSG("Error executing regex: %s", err);
                        } else {
                                uint64_t config = 0;
                                uint64_t event = 0;
                                if (snprintf(fpga_perf->perf_events[inner_loop].event_name,
                                        sizeof(fpga_perf->perf_events[inner_loop].event_name),
                                        "%s", (strstr(pglob.gl_pathv[i], attr)
                                                + strlen(attr) + 1)) < 0) {
                                        OPAE_ERR("snprintf buffer overflow");
                                        goto out;
                                }
                                for (loop = 0; loop < fpga_perf->num_format; loop++) {
                                        PARSE_MATCH_INT(attr_value,
                                                e_matches[loop + 1].rm_so, event, 16);
                                        config |= event << fpga_perf->format_type[loop].shift;
                                }
                                fpga_perf->perf_events[inner_loop].config = config;
                                inner_loop++;
                        }
                }
                fclose(file);
        }

        globfree(&pglob);
        return FPGA_OK;

out:
        fclose(file);
        globfree(&pglob);
        return FPGA_EXCEPTION;
}

STATIC fpga_result fpga_perf_events(char* perf_sysfs_path, fpga_perf_counter *fpga_perf)
{
        fpga_result ret         = FPGA_OK;
        struct udev *udev         = NULL;
        struct udev_device *dev = NULL;
        int fd                         = 0;
        int grpfd                = 0;
        uint64_t loop                 = 0;
        struct perf_event_attr pea;
        
        if (!perf_sysfs_path || !fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }
        /* create udev object */
        udev = udev_new();
        if (!udev) {
                OPAE_ERR("Cannot create udev context");
                return FPGA_EXCEPTION;
        }
        dev = udev_device_new_from_syspath(udev, perf_sysfs_path);
        if (!dev) {
                OPAE_ERR("Failed to get device");
                udev_unref(udev);
                return FPGA_EXCEPTION;
        }
        const char * ptr = udev_device_get_sysattr_value(dev, "cpumask");
        if (ptr)
                PARSE_MATCH_INT(ptr, 0, fpga_perf->cpumask, 10);
        ptr = udev_device_get_sysattr_value(dev, "type");
        if (ptr)
                PARSE_MATCH_INT(ptr, 0, fpga_perf->type, 10);

        /* parse the format value */
        ret = parse_perf_attributes(dev, fpga_perf, "format");
        if (ret != FPGA_OK)
                goto out;
        /* parse the event value */
        ret = parse_perf_attributes(dev, fpga_perf, "events");
        if (ret != FPGA_OK)
                goto out;

        /* initialize the pea structure to 0 */
        memset(&pea, 0, sizeof(struct perf_event_attr));

        for (loop = 0; loop < fpga_perf->num_perf_events; loop++) {

                if (fpga_perf->perf_events[0].fd <= 0)
                        grpfd = -1;
                else
                        grpfd = fpga_perf->perf_events[0].fd;
                
                if (!fpga_perf->perf_events[loop].config)
                        continue;

                pea.type = fpga_perf->type;
                pea.size = sizeof(struct perf_event_attr);
                pea.config = fpga_perf->perf_events[loop].config;
                pea.disabled = 1;
                pea.inherit = 1;
                pea.sample_type = PERF_SAMPLE_IDENTIFIER;
                pea.read_format = PERF_FORMAT_GROUP | PERF_FORMAT_ID;
                fd = syscall(__NR_perf_event_open, &pea, -1, fpga_perf->cpumask, grpfd, 0);
                if (fd == -1) {
                        OPAE_ERR("Error opening leader %llx\n", pea.config);
                        ret = FPGA_EXCEPTION;
                        goto out;
                } else {
                        fpga_perf->perf_events[loop].fd = fd;
                        if (ioctl(fpga_perf->perf_events[loop].fd, PERF_EVENT_IOC_ID,
                                                &fpga_perf->perf_events[loop].id) == -1) {
                                OPAE_ERR("PERF_EVENT_IOC_ID ioctl failed: %s",
                                                strerror(errno));
                                ret = FPGA_EXCEPTION;
                                goto out;
                        }
                }
        }
        if (ioctl(fpga_perf->perf_events[0].fd, PERF_EVENT_IOC_RESET,
                                PERF_IOC_FLAG_GROUP) == -1) {
                OPAE_ERR("PERF_EVENT_IOC_RESET ioctl failed: %s", strerror(errno));
                ret = FPGA_EXCEPTION;
                goto out;
        }
out:
        udev_device_unref(dev);
        udev_unref(udev);
        return ret;
}

/* get fpga sbdf from token */
STATIC fpga_result get_fpga_sbdf(fpga_token token,
                uint16_t *segment,
                uint8_t *bus,
                uint8_t *device,
                uint8_t *function)
{
        fpga_result res                = FPGA_OK;
        fpga_properties props        = NULL;

        if (!segment || !bus ||
                !device || !function) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }
        res = fpgaGetProperties(token, &props);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get properties");
                return res;
        }
        res = fpgaPropertiesGetBus(props, bus);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get bus");
                return res;
        }
        res = fpgaPropertiesGetSegment(props, segment);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get Segment");
                return res;
        }
        res = fpgaPropertiesGetDevice(props, device);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get Device");
                return res;
        }
        res = fpgaPropertiesGetFunction(props, function);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get Function");
                return res;
        }

        return res;
}

/* Initialises magic number, mutex attributes and set the mutex attribute
 * type to PTHREAD_MUTEX_RECURSIVE. Also initialises the mutex referenced by
 * fpga_perf->lock with attributes specified by mutex attributes */
STATIC fpga_result fpga_perf_mutex_init(fpga_perf_counter *fpga_perf)
{
        pthread_mutexattr_t mattr;

        if (!fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }

        fpga_perf->magic = FPGA_PERF_MAGIC;

        if (pthread_mutexattr_init(&mattr)) {
                OPAE_ERR("pthread_mutexattr_init() failed");
                return FPGA_EXCEPTION;
        }

        if (pthread_mutexattr_settype(&mattr, PTHREAD_MUTEX_RECURSIVE)) {
                OPAE_ERR("pthread_mutexattr_settype() failed");
                pthread_mutexattr_destroy(&mattr);
                return FPGA_EXCEPTION;
        }

        if (pthread_mutex_init(&fpga_perf->lock, &mattr)) {
                OPAE_ERR("pthread_mutex_init() failed");
                pthread_mutexattr_destroy(&mattr);
                return FPGA_EXCEPTION;
        }
        pthread_mutexattr_destroy(&mattr);

        return FPGA_OK;
}

/* Reset the magic number and destroy the mutex created */
STATIC fpga_result fpga_perf_mutex_destroy(fpga_perf_counter *fpga_perf)
{
        fpga_result ret = FPGA_OK;
        int res                = 0;

        if (!fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }

        ret = fpga_perf_check_and_lock(fpga_perf);
        if (ret) {
                OPAE_ERR("Failed to lock perf mutex");
                return ret;
        }

        fpga_perf->magic = 0;

        ret = opae_mutex_unlock(res, &fpga_perf->lock);
        if (ret) {
                OPAE_ERR("Failed to unlock perf mutex");
                return ret;
        }

        ret = pthread_mutex_destroy(&fpga_perf->lock);
        if (ret) {
                OPAE_ERR("Failed to destroy pthread mutex destroy");
                return ret;
        }

        return FPGA_OK;
}


fpga_result fpgaPerfCounterGet(fpga_token token, fpga_perf_counter *fpga_perf)
{
        fpga_result ret                                = FPGA_OK;
        int res                                        = 0;
        char sysfs_path[DFL_PERF_STR_MAX]        = { 0 };
        char sysfs_perf[DFL_PERF_STR_MAX]        = { 0 };
        int gres                                 = 0;
        uint32_t fpga_id                         = -1;
        char *endptr                                 = NULL;
        glob_t pglob;
        uint8_t bus                                = (uint8_t)-1;
        uint16_t segment                        = (uint16_t)-1;
        uint8_t device                                = (uint8_t)-1;
        uint8_t function                        = (uint8_t)-1;


        if (!token || !fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }

        memset(fpga_perf, 0, sizeof(fpga_perf_counter));

        ret = get_fpga_sbdf(token, &segment, &bus, &device, &function);
        if (ret != FPGA_OK) {
                OPAE_ERR("Failed to get sbdf");
                return ret;
        }
        ret = fpga_perf_mutex_init(fpga_perf);
        if (ret != FPGA_OK) {
                OPAE_ERR("Failed to initialize the mutex");
                return ret;
        }

        /* when we bind with new device id we will get updated function value */
        /* not able to read the sysfs path using that */
        if(function)
                function = 0;
        if (snprintf(sysfs_path, sizeof(sysfs_path),
                DFL_PERF_FME,
                segment, bus, device, function) < 0) {
                OPAE_ERR("snprintf buffer overflow");
                return FPGA_EXCEPTION;
        }

        gres = glob(sysfs_path, GLOB_NOSORT, NULL, &pglob);
        if (gres) {
                OPAE_ERR("Failed pattern match %s: %s", sysfs_path, strerror(errno));
                globfree(&pglob);
                return FPGA_NOT_FOUND;
        }        

        if (pglob.gl_pathc == 1) {
                char *ptr = strstr(pglob.gl_pathv[0], "fme");
                if (!ptr) {
                        ret = FPGA_INVALID_PARAM;
                        goto out;
                }
                errno = 0;
                fpga_id = strtoul(ptr + 4, &endptr, 10);

                if (snprintf(sysfs_perf, sizeof(sysfs_perf),
                        DFL_PERF_SYSFS"%d", fpga_id) < 0) {
                        OPAE_ERR("snprintf buffer overflow");
                        ret = FPGA_EXCEPTION;
                        goto out;
                }
                if (fpga_perf_check_and_lock(fpga_perf)) {
                        OPAE_ERR("Failed to lock perf mutex");
                        ret = FPGA_EXCEPTION;
                        goto out;
                }
                if (snprintf(fpga_perf->dfl_fme_name, sizeof(fpga_perf->dfl_fme_name),
                        "dfl_fme%d", fpga_id) < 0) {
                        OPAE_ERR("snprintf buffer overflow");
                        opae_mutex_unlock(res, &fpga_perf->lock);
                        ret = FPGA_EXCEPTION;
                        goto out;
                }
                ret = fpga_perf_events(sysfs_perf, fpga_perf);
                if (ret != FPGA_OK) {
                        OPAE_ERR("Failed to parse fpga perf event");
                        opae_mutex_unlock(res, &fpga_perf->lock);
                        goto out;
                }
                if (opae_mutex_unlock(res, &fpga_perf->lock)) {
                        OPAE_ERR("Failed to unlock perf mutex");
                        ret = FPGA_EXCEPTION;
                        goto out;
                }        
        } else {
                ret = FPGA_NOT_FOUND;
                goto out;
        }
out:
        globfree(&pglob);
        return ret;
}

fpga_result fpgaPerfCounterStartRecord(fpga_perf_counter *fpga_perf)
{
        uint64_t loop                        = 0;
        uint64_t inner_loop                = 0;
        int res                                = 0;
        char buf[DFL_PERF_STR_MAX]        = { 0 };
        struct read_format *rdft        = (struct read_format *) buf;

        if (!fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }

        if (fpga_perf_check_and_lock(fpga_perf)) {
                OPAE_ERR("Failed to lock perf mutex");
                return FPGA_EXCEPTION;
        }
        if (ioctl(fpga_perf->perf_events[0].fd, PERF_EVENT_IOC_ENABLE,
                                PERF_IOC_FLAG_GROUP) == -1) {
                OPAE_ERR("PERF_EVENT_IOC_ENABLE ioctl failed: %s",
                                strerror(errno));
                goto out;
        }
        if (read(fpga_perf->perf_events[0].fd, rdft, sizeof(buf)) == -1) {
                OPAE_ERR("read fpga perf counter failed");
                goto out;
        }
        for (loop = 0; loop < (uint64_t)rdft->nr; loop++) {
                for (inner_loop = 0; inner_loop < fpga_perf->num_perf_events;
                                                                inner_loop++) {
                        if (rdft->values[loop].id == fpga_perf->perf_events[inner_loop].id)
                                fpga_perf->perf_events[inner_loop].start_value = rdft->values[loop].value;
                }
        }        
        if (opae_mutex_unlock(res, &fpga_perf->lock)) {
                OPAE_ERR("Failed to unlock perf mutex");
                return FPGA_EXCEPTION;
        }
        return FPGA_OK;
out:
        opae_mutex_unlock(res, &fpga_perf->lock);
        return FPGA_EXCEPTION;
}

fpga_result fpgaPerfCounterStopRecord(fpga_perf_counter *fpga_perf)
{
        char buf[DFL_PERF_STR_MAX]        = { 0 };
        uint64_t loop                        = 0;
        uint64_t inner_loop                = 0;
        int res                                = 0;
        struct read_format *rdft         = (struct read_format *) buf;

        if (!fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }

        if (fpga_perf_check_and_lock(fpga_perf)) {
                OPAE_ERR("Failed to lock perf mutex");
                return FPGA_EXCEPTION;
        }
        if (ioctl(fpga_perf->perf_events[0].fd, PERF_EVENT_IOC_DISABLE,
                                PERF_IOC_FLAG_GROUP) == -1) {
                OPAE_ERR("PERF_EVENT_IOC_ENABLE ioctl failed: %s",
                                strerror(errno));
                goto out;
        }
        if (read(fpga_perf->perf_events[0].fd, rdft, sizeof(buf)) == -1) {
                OPAE_ERR("read fpga perf counter failed");
                goto out;
        }        
        for (loop = 0; loop < (uint64_t)rdft->nr; loop++) {
                for (inner_loop = 0; inner_loop < fpga_perf->num_perf_events;
                                                                inner_loop++) {
                        if (rdft->values[loop].id == fpga_perf->perf_events[inner_loop].id)
                                fpga_perf->perf_events[inner_loop].stop_value = rdft->values[loop].value;
                }
        }
        if (opae_mutex_unlock(res, &fpga_perf->lock)) {
                OPAE_ERR("Failed to unlock perf mutex");
                return FPGA_EXCEPTION;
        }
        return FPGA_OK;
out:
        opae_mutex_unlock(res, &fpga_perf->lock);
        return FPGA_EXCEPTION;
}

fpga_result fpgaPerfCounterPrint(FILE *f, fpga_perf_counter *fpga_perf)
{
        uint64_t loop         = 0;
        int res                = 0;

        if (!fpga_perf || !f) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }

        if (fpga_perf_check_and_lock(fpga_perf)) {
                OPAE_ERR("Failed to lock perf mutex");
                return FPGA_EXCEPTION;
        }

        fprintf(f, "\n");
        for (loop = 0; loop < fpga_perf->num_perf_events; loop++)
                fprintf(f, "%s\t", fpga_perf->perf_events[loop].event_name);

        fprintf(f, "\n");
        for (loop = 0; loop < fpga_perf->num_perf_events; loop++) {
                if (!fpga_perf->perf_events[loop].config)
                        continue;
                fprintf(f, "%ld\t\t", (fpga_perf->perf_events[loop].stop_value
                                - fpga_perf->perf_events[loop].start_value));
        }

        fprintf(f, "\n");

        if (opae_mutex_unlock(res, &fpga_perf->lock)) {
                OPAE_ERR("Failed to unlock perf mutex");
                return FPGA_EXCEPTION;
        }

        return FPGA_OK;
}

fpga_result fpgaPerfCounterDestroy(fpga_perf_counter *fpga_perf)
{
        int res        = 0;

        if (!fpga_perf) {
                OPAE_ERR("Invalid input parameters");
                return FPGA_INVALID_PARAM;
        }
        if (fpga_perf_check_and_lock(fpga_perf)) {
                OPAE_ERR("Failed to lock perf mutex");
                return FPGA_EXCEPTION;
        }
        if (fpga_perf->format_type) {
                free(fpga_perf->format_type);
                fpga_perf->format_type = NULL;
        }
        if (fpga_perf->perf_events) {
                free(fpga_perf->perf_events);
                fpga_perf->perf_events = NULL;
        }

        if (opae_mutex_unlock(res, &fpga_perf->lock)) {
                OPAE_ERR("Failed to unlock perf mutex");
                return FPGA_EXCEPTION;
        }
        if (fpga_perf_mutex_destroy(fpga_perf) != FPGA_OK) {
                OPAE_ERR("Failed to destroy the mutex");
                return FPGA_EXCEPTION;
        }

        return FPGA_OK;
}

1	// Copyright(c) 2021, Intel Corporation
2	//
3	// Redistribution and use in source and binary forms, with or without
4	// modification, are permitted provided that the following conditions are met:
5	//
6	// * Redistributions of source code must retain the above copyright notice,
7	// this list of conditions and the following disclaimer.
8	// * Redistributions in binary form must reproduce the above copyright notice,
9	// this list of conditions and the following disclaimer in the documentation
10	// and/or other materials provided with the distribution.
11	// * Neither the name of Intel Corporation nor the names of its contributors
12	// may be used to endorse or promote products derived from this software
13	// without specific prior written permission.
14	//
15	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16	// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19	// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20	// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21	// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22	// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23	// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24	// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25	// POSSIBILITY OF SUCH DAMAGE.
26
27	#include "fpgaperf_counter.h"
28
29	#include <errno.h>
30	#include <glob.h>
31	#include <regex.h>
32	#include <stdlib.h>
33	#include <stdint.h>
34	#include <string.h>
35	#include <unistd.h>
36	#include <sys/ioctl.h>
37	#include <sys/syscall.h>
38	#include <libudev.h>
39	#include <linux/perf_event.h>
40
41	#include <opae/fpga.h>
42	#include <opae/log.h>
43	#include <opae/properties.h>
44	#include <opae/utils.h>
45	#include "opae_int.h"
46
47	#define PCI_DEV_ADDRS "/sys/bus/pci/devices/%x:%x:%x.%x/"
48
49	#define DFL_PERF_FME PCI_DEV_ADDRS "fpga_region/region/dfl-fme."
50
51	#define DFL_PERF_SYSFS "/sys/bus/event_source/devices/dfl_fme"
52
53	#define PERF_EVENT "event=(0x[0-9a-fA-F]{2}),"
54
55	#define PERF_EVTYPE "evtype=(0x[0-9a-fA-F]{2}),"
56
57	#define PERF_PORTID "portid=(0x[0-9a-fA-F]{2})"
58
59	#define PERF_EVENT_PATTERN PERF_EVENT PERF_EVTYPE PERF_PORTID
60
61	#define PERF_CONFIG_PATTERN "config:([0-9]{1,})-([0-9]{2,})"
62
63	#define PARSE_MATCH_INT(_p, _m, _v, _b) \
64	do { \
65	errno = 0; \
66	_v = strtoul(_p + _m, NULL, _b); \
67	if (errno) { \
68	OPAE_MSG("error parsing int"); \
69	} \
70	} while (0)
71
72
73	/* Read format structure*/
74	struct read_format {
75	uint64_t nr;
76	struct {
77	uint64_t value;
78	uint64_t id;
79	} values[];
80	};
81
82	/*
83	* Check perf handle object for validity and lock its mutex
84	* If fpga_perf_check_and_lock() returns FPGA_OK, assume the mutex to be
85	* locked.
86	*/
87	STATIC fpga_result fpga_perf_check_and_lock(fpga_perf_counter *fpga_perf)	×
88	{
89	int res = 0;	×
90
91	if (!fpga_perf)	×
92	return FPGA_INVALID_PARAM;	×
93
94	if (opae_mutex_lock(res, &fpga_perf->lock)) {	×
95	OPAE_ERR("Failed to lock perf mutex");	×
96	return FPGA_EXCEPTION;	×
97	}
98
99	if (fpga_perf->magic != FPGA_PERF_MAGIC) {	×
100	opae_mutex_unlock(res, &fpga_perf->lock);	×
101	return FPGA_INVALID_PARAM;	×
102	}
103
104	return FPGA_OK;	×
105	}
106
107	/* parse the each format and get the shift val
108	* parse the events for the particular device directory */
109	STATIC fpga_result parse_perf_attributes(struct udev_device *dev,	×
110	fpga_perf_counter fpga_perf, const char attr)
111	{
112	regex_t re;
113	char err[128] = { 0 };	×
114	int reg_res = 0;	×
115	uint64_t loop = 0;	×
116	uint64_t inner_loop = 0;	×
117	uint64_t value = 0;	×
118	char attr_path[DFL_PERF_STR_MAX] = { 0,};	×
119	char attr_value[128] = { 0,};	×
120	int gres = 0;	×
121	size_t i = 0;	×
122	FILE *file = NULL;	×
123	glob_t pglob;
124	regmatch_t f_matches[3] = { {0} };	×
125	regmatch_t e_matches[4] = { {0} };	×
126
127	if (!dev \|\| !fpga_perf) {	×
128	OPAE_ERR("Invalid input parameters");	×
129	return FPGA_INVALID_PARAM;	×
130	}
131
132	if (snprintf(attr_path, sizeof(attr_path), "%s/%s/*",	×
133	udev_device_get_syspath(dev), attr) < 0) {
134	OPAE_ERR("snprintf buffer overflow");	×
135	return FPGA_EXCEPTION;	×
136	}
137	gres = glob(attr_path, GLOB_NOSORT, NULL, &pglob);	×
138	if (gres \|\| !pglob.gl_pathc) {	×
139	OPAE_ERR("Failed pattern match %s", attr_path);	×
140	globfree(&pglob);	×
141	return FPGA_EXCEPTION;	×
142	}
143	if (strcmp(attr, "format") == 0 ) {	×
144	fpga_perf->num_format = pglob.gl_pathc;	×
145	if (!fpga_perf->format_type) {	×
146	fpga_perf->format_type = calloc(fpga_perf->num_format,	×
147	sizeof(perf_format_type));
148	if (!fpga_perf->format_type) {	×
149	fpga_perf->num_format = 0;	×
150	OPAE_ERR("Failed to allocate Memory");	×
151	globfree(&pglob);	×
152	return FPGA_NO_MEMORY;	×
153	}
154	}
155	} else {
156	fpga_perf->num_perf_events = pglob.gl_pathc;	×
157	if (!fpga_perf->perf_events) {	×
158	fpga_perf->perf_events = calloc(fpga_perf->num_perf_events,	×
159	sizeof(perf_events_type));
160	if (!fpga_perf->perf_events) {	×
161	fpga_perf->num_perf_events = 0;	×
162	OPAE_ERR("Failed to allocate Memory");	×
163	globfree(&pglob);	×
164	return FPGA_NO_MEMORY;	×
165	}
166	}
167	}
168
169	for (i = 0; i < pglob.gl_pathc; i++) {	×
170	file = fopen(pglob.gl_pathv[i], "r");	×
171	if (!file) {	×
172	OPAE_ERR("fopen(%s) failed\n", pglob.gl_pathv[i]);	×
173	globfree(&pglob);	×
174	return FPGA_EXCEPTION;	×
175	}
176	if (fscanf(file, "%127s", attr_value) != 1) {	×
177	OPAE_ERR("Failed to read %s", pglob.gl_pathv[i]);	×
178	goto out;	×
179	}
180	if (strcmp(attr, "format") == 0 ) {	×
181	reg_res = regcomp(&re, PERF_CONFIG_PATTERN,	×
182	REG_EXTENDED \| REG_ICASE);
183	if (reg_res) {	×
184	OPAE_ERR("Error compiling regex");	×
185	goto out;	×
186	}
187	reg_res = regexec(&re, attr_value, 4, f_matches, 0);	×
188	if (reg_res) {	×
189	regerror(reg_res, &re, err, sizeof(err));	×
190	OPAE_MSG("Error executing regex: %s", err);	×
191	} else {
192	PARSE_MATCH_INT(attr_value, f_matches[1].rm_so, value, 10);	×
193	fpga_perf->format_type[loop].shift = value;	×
194	if (snprintf(fpga_perf->format_type[loop].format_name,	×
195	sizeof(fpga_perf->format_type[loop].format_name),
196	"%s", (strstr(pglob.gl_pathv[i], attr)	×
197	+ strlen(attr)+1)) < 0) {	×
198	OPAE_ERR("snprintf buffer overflow");	×
199	goto out;	×
200	}
201	loop++;	×
202	}
203	} else {
204	reg_res = regcomp(&re, PERF_EVENT_PATTERN,	×
205	REG_EXTENDED \| REG_ICASE);
206	if (reg_res) {	×
207	OPAE_ERR("Error compiling regex");	×
208	goto out;	×
209	}
210	reg_res = regexec(&re, attr_value, 4, e_matches, 0);	×
211	if (reg_res) {	×
212	regerror(reg_res, &re, err, sizeof(err));	×
213	OPAE_MSG("Error executing regex: %s", err);	×
214	} else {
215	uint64_t config = 0;	×
216	uint64_t event = 0;	×
217	if (snprintf(fpga_perf->perf_events[inner_loop].event_name,	×
218	sizeof(fpga_perf->perf_events[inner_loop].event_name),
219	"%s", (strstr(pglob.gl_pathv[i], attr)	×
220	+ strlen(attr) + 1)) < 0) {	×
221	OPAE_ERR("snprintf buffer overflow");	×
222	goto out;	×
223	}
224	for (loop = 0; loop < fpga_perf->num_format; loop++) {	×
225	PARSE_MATCH_INT(attr_value,	×
226	e_matches[loop + 1].rm_so, event, 16);
227	config \|= event << fpga_perf->format_type[loop].shift;	×
228	}
229	fpga_perf->perf_events[inner_loop].config = config;	×
230	inner_loop++;	×
231	}
232	}
233	fclose(file);	×
234	}
235
236	globfree(&pglob);	×
237	return FPGA_OK;	×
238
239	out:	×
240	fclose(file);	×
241	globfree(&pglob);	×
242	return FPGA_EXCEPTION;	×
243	}
244
245	STATIC fpga_result fpga_perf_events(char* perf_sysfs_path, fpga_perf_counter *fpga_perf)	×
246	{
247	fpga_result ret = FPGA_OK;	×
248	struct udev *udev = NULL;	×
249	struct udev_device *dev = NULL;	×
250	int fd = 0;	×
251	int grpfd = 0;	×
252	uint64_t loop = 0;	×
253	struct perf_event_attr pea;
254
255	if (!perf_sysfs_path \|\| !fpga_perf) {	×
256	OPAE_ERR("Invalid input parameters");	×
257	return FPGA_INVALID_PARAM;	×
258	}
259	/* create udev object */
260	udev = udev_new();	×
261	if (!udev) {	×
262	OPAE_ERR("Cannot create udev context");	×
263	return FPGA_EXCEPTION;	×
264	}
265	dev = udev_device_new_from_syspath(udev, perf_sysfs_path);	×
266	if (!dev) {	×
267	OPAE_ERR("Failed to get device");	×
268	udev_unref(udev);	×
269	return FPGA_EXCEPTION;	×
270	}
271	const char * ptr = udev_device_get_sysattr_value(dev, "cpumask");	×
272	if (ptr)	×
273	PARSE_MATCH_INT(ptr, 0, fpga_perf->cpumask, 10);	×
274	ptr = udev_device_get_sysattr_value(dev, "type");	×
275	if (ptr)	×
276	PARSE_MATCH_INT(ptr, 0, fpga_perf->type, 10);	×
277
278	/* parse the format value */
279	ret = parse_perf_attributes(dev, fpga_perf, "format");	×
280	if (ret != FPGA_OK)	×
281	goto out;	×
282	/* parse the event value */
283	ret = parse_perf_attributes(dev, fpga_perf, "events");	×
284	if (ret != FPGA_OK)	×
285	goto out;	×
286
287	/* initialize the pea structure to 0 */
288	memset(&pea, 0, sizeof(struct perf_event_attr));	×
289
290	for (loop = 0; loop < fpga_perf->num_perf_events; loop++) {	×
291
292	if (fpga_perf->perf_events[0].fd <= 0)	×
293	grpfd = -1;	×
294	else
295	grpfd = fpga_perf->perf_events[0].fd;	×
296
297	if (!fpga_perf->perf_events[loop].config)	×
298	continue;	×
299
300	pea.type = fpga_perf->type;	×
301	pea.size = sizeof(struct perf_event_attr);	×
302	pea.config = fpga_perf->perf_events[loop].config;	×
303	pea.disabled = 1;	×
304	pea.inherit = 1;	×
305	pea.sample_type = PERF_SAMPLE_IDENTIFIER;	×
306	pea.read_format = PERF_FORMAT_GROUP \| PERF_FORMAT_ID;	×
307	fd = syscall(__NR_perf_event_open, &pea, -1, fpga_perf->cpumask, grpfd, 0);	×
308	if (fd == -1) {	×
309	OPAE_ERR("Error opening leader %llx\n", pea.config);	×
310	ret = FPGA_EXCEPTION;	×
311	goto out;	×
312	} else {
313	fpga_perf->perf_events[loop].fd = fd;	×
314	if (ioctl(fpga_perf->perf_events[loop].fd, PERF_EVENT_IOC_ID,	×
315	&fpga_perf->perf_events[loop].id) == -1) {	×
316	OPAE_ERR("PERF_EVENT_IOC_ID ioctl failed: %s",	×
317	strerror(errno));
318	ret = FPGA_EXCEPTION;	×
319	goto out;	×
320	}
321	}
322	}
323	if (ioctl(fpga_perf->perf_events[0].fd, PERF_EVENT_IOC_RESET,	×
324	PERF_IOC_FLAG_GROUP) == -1) {
325	OPAE_ERR("PERF_EVENT_IOC_RESET ioctl failed: %s", strerror(errno));	×
326	ret = FPGA_EXCEPTION;	×
327	goto out;	×
328	}
329	out:	×
330	udev_device_unref(dev);	×
331	udev_unref(udev);	×
332	return ret;	×
333	}
334
335	/* get fpga sbdf from token */
336	STATIC fpga_result get_fpga_sbdf(fpga_token token,	×
337	uint16_t *segment,
338	uint8_t *bus,
339	uint8_t *device,
340	uint8_t *function)
341	{
342	fpga_result res = FPGA_OK;	×
343	fpga_properties props = NULL;	×
344
345	if (!segment \|\| !bus \|\|	×
346	!device \|\| !function) {	×
347	OPAE_ERR("Invalid input parameters");	×
348	return FPGA_INVALID_PARAM;	×
349	}
350	res = fpgaGetProperties(token, &props);	×
351	if (res != FPGA_OK) {	×
352	OPAE_ERR("Failed to get properties");	×
353	return res;	×
354	}
355	res = fpgaPropertiesGetBus(props, bus);	×
356	if (res != FPGA_OK) {	×
357	OPAE_ERR("Failed to get bus");	×
358	return res;	×
359	}
360	res = fpgaPropertiesGetSegment(props, segment);	×
361	if (res != FPGA_OK) {	×
362	OPAE_ERR("Failed to get Segment");	×
363	return res;	×
364	}
365	res = fpgaPropertiesGetDevice(props, device);	×
366	if (res != FPGA_OK) {	×
367	OPAE_ERR("Failed to get Device");	×
368	return res;	×
369	}
370	res = fpgaPropertiesGetFunction(props, function);	×
371	if (res != FPGA_OK) {	×
372	OPAE_ERR("Failed to get Function");	×
373	return res;	×
374	}
375
376	return res;	×
377	}
378
379	/* Initialises magic number, mutex attributes and set the mutex attribute
380	* type to PTHREAD_MUTEX_RECURSIVE. Also initialises the mutex referenced by
381	* fpga_perf->lock with attributes specified by mutex attributes */
382	STATIC fpga_result fpga_perf_mutex_init(fpga_perf_counter *fpga_perf)	×
383	{
384	pthread_mutexattr_t mattr;
385
386	if (!fpga_perf) {	×
387	OPAE_ERR("Invalid input parameters");	×
388	return FPGA_INVALID_PARAM;	×
389	}
390
391	fpga_perf->magic = FPGA_PERF_MAGIC;	×
392
393	if (pthread_mutexattr_init(&mattr)) {	×
394	OPAE_ERR("pthread_mutexattr_init() failed");	×
395	return FPGA_EXCEPTION;	×
396	}
397
398	if (pthread_mutexattr_settype(&mattr, PTHREAD_MUTEX_RECURSIVE)) {	×
399	OPAE_ERR("pthread_mutexattr_settype() failed");	×
400	pthread_mutexattr_destroy(&mattr);	×
401	return FPGA_EXCEPTION;	×
402	}
403
404	if (pthread_mutex_init(&fpga_perf->lock, &mattr)) {	×
405	OPAE_ERR("pthread_mutex_init() failed");	×
406	pthread_mutexattr_destroy(&mattr);	×
407	return FPGA_EXCEPTION;	×
408	}
409	pthread_mutexattr_destroy(&mattr);	×
410
411	return FPGA_OK;	×
412	}
413
414	/* Reset the magic number and destroy the mutex created */
415	STATIC fpga_result fpga_perf_mutex_destroy(fpga_perf_counter *fpga_perf)	×
416	{
417	fpga_result ret = FPGA_OK;	×
418	int res = 0;	×
419
420	if (!fpga_perf) {	×
421	OPAE_ERR("Invalid input parameters");	×
422	return FPGA_INVALID_PARAM;	×
423	}
424
425	ret = fpga_perf_check_and_lock(fpga_perf);	×
426	if (ret) {	×
427	OPAE_ERR("Failed to lock perf mutex");	×
428	return ret;	×
429	}
430
431	fpga_perf->magic = 0;	×
432
433	ret = opae_mutex_unlock(res, &fpga_perf->lock);	×
434	if (ret) {	×
435	OPAE_ERR("Failed to unlock perf mutex");	×
436	return ret;	×
437	}
438
439	ret = pthread_mutex_destroy(&fpga_perf->lock);	×
440	if (ret) {	×
441	OPAE_ERR("Failed to destroy pthread mutex destroy");	×
442	return ret;	×
443	}
444
445	return FPGA_OK;	×
446	}
447
448
449	fpga_result fpgaPerfCounterGet(fpga_token token, fpga_perf_counter *fpga_perf)	×
450	{
451	fpga_result ret = FPGA_OK;	×
452	int res = 0;	×
453	char sysfs_path[DFL_PERF_STR_MAX] = { 0 };	×
454	char sysfs_perf[DFL_PERF_STR_MAX] = { 0 };	×
455	int gres = 0;	×
456	uint32_t fpga_id = -1;	×
457	char *endptr = NULL;	×
458	glob_t pglob;
459	uint8_t bus = (uint8_t)-1;	×
460	uint16_t segment = (uint16_t)-1;	×
461	uint8_t device = (uint8_t)-1;	×
462	uint8_t function = (uint8_t)-1;	×
463
464
465	if (!token \|\| !fpga_perf) {	×
466	OPAE_ERR("Invalid input parameters");	×
467	return FPGA_INVALID_PARAM;	×
468	}
469
470	memset(fpga_perf, 0, sizeof(fpga_perf_counter));	×
471
472	ret = get_fpga_sbdf(token, &segment, &bus, &device, &function);	×
473	if (ret != FPGA_OK) {	×
474	OPAE_ERR("Failed to get sbdf");	×
475	return ret;	×
476	}
477	ret = fpga_perf_mutex_init(fpga_perf);	×
478	if (ret != FPGA_OK) {	×
479	OPAE_ERR("Failed to initialize the mutex");	×
480	return ret;	×
481	}
482
483	/* when we bind with new device id we will get updated function value */
484	/* not able to read the sysfs path using that */
485	if(function)	×
486	function = 0;	×
487	if (snprintf(sysfs_path, sizeof(sysfs_path),	×
488	DFL_PERF_FME,
489	segment, bus, device, function) < 0) {
490	OPAE_ERR("snprintf buffer overflow");	×
491	return FPGA_EXCEPTION;	×
492	}
493
494	gres = glob(sysfs_path, GLOB_NOSORT, NULL, &pglob);	×
495	if (gres) {	×
496	OPAE_ERR("Failed pattern match %s: %s", sysfs_path, strerror(errno));	×
497	globfree(&pglob);	×
498	return FPGA_NOT_FOUND;	×
499	}
500
501	if (pglob.gl_pathc == 1) {	×
502	char *ptr = strstr(pglob.gl_pathv[0], "fme");	×
503	if (!ptr) {	×
504	ret = FPGA_INVALID_PARAM;	×
505	goto out;	×
506	}
507	errno = 0;	×
508	fpga_id = strtoul(ptr + 4, &endptr, 10);	×
509
510	if (snprintf(sysfs_perf, sizeof(sysfs_perf),	×
511	DFL_PERF_SYSFS"%d", fpga_id) < 0) {
512	OPAE_ERR("snprintf buffer overflow");	×
513	ret = FPGA_EXCEPTION;	×
514	goto out;	×
515	}
516	if (fpga_perf_check_and_lock(fpga_perf)) {	×
517	OPAE_ERR("Failed to lock perf mutex");	×
518	ret = FPGA_EXCEPTION;	×
519	goto out;	×
520	}
521	if (snprintf(fpga_perf->dfl_fme_name, sizeof(fpga_perf->dfl_fme_name),	×
522	"dfl_fme%d", fpga_id) < 0) {
523	OPAE_ERR("snprintf buffer overflow");	×
524	opae_mutex_unlock(res, &fpga_perf->lock);	×
525	ret = FPGA_EXCEPTION;	×
526	goto out;	×
527	}
528	ret = fpga_perf_events(sysfs_perf, fpga_perf);	×
529	if (ret != FPGA_OK) {	×
530	OPAE_ERR("Failed to parse fpga perf event");	×
531	opae_mutex_unlock(res, &fpga_perf->lock);	×
532	goto out;	×
533	}
534	if (opae_mutex_unlock(res, &fpga_perf->lock)) {	×
535	OPAE_ERR("Failed to unlock perf mutex");	×
536	ret = FPGA_EXCEPTION;	×
537	goto out;	×
538	}
539	} else {
540	ret = FPGA_NOT_FOUND;	×
541	goto out;	×
542	}
543	out:	×
544	globfree(&pglob);	×
545	return ret;	×
546	}
547
548	fpga_result fpgaPerfCounterStartRecord(fpga_perf_counter *fpga_perf)	×
549	{
550	uint64_t loop = 0;	×
551	uint64_t inner_loop = 0;	×
552	int res = 0;	×
553	char buf[DFL_PERF_STR_MAX] = { 0 };	×
554	struct read_format rdft = (struct read_format ) buf;	×
555
556	if (!fpga_perf) {	×
557	OPAE_ERR("Invalid input parameters");	×
558	return FPGA_INVALID_PARAM;	×
559	}
560
561	if (fpga_perf_check_and_lock(fpga_perf)) {	×
562	OPAE_ERR("Failed to lock perf mutex");	×
563	return FPGA_EXCEPTION;	×
564	}
565	if (ioctl(fpga_perf->perf_events[0].fd, PERF_EVENT_IOC_ENABLE,	×
566	PERF_IOC_FLAG_GROUP) == -1) {
567	OPAE_ERR("PERF_EVENT_IOC_ENABLE ioctl failed: %s",	×
568	strerror(errno));
569	goto out;	×
570	}
571	if (read(fpga_perf->perf_events[0].fd, rdft, sizeof(buf)) == -1) {	×
572	OPAE_ERR("read fpga perf counter failed");	×
573	goto out;	×
574	}
575	for (loop = 0; loop < (uint64_t)rdft->nr; loop++) {	×
576	for (inner_loop = 0; inner_loop < fpga_perf->num_perf_events;	×
577	inner_loop++) {	×
578	if (rdft->values[loop].id == fpga_perf->perf_events[inner_loop].id)	×
579	fpga_perf->perf_events[inner_loop].start_value = rdft->values[loop].value;	×
580	}
581	}
582	if (opae_mutex_unlock(res, &fpga_perf->lock)) {	×
583	OPAE_ERR("Failed to unlock perf mutex");	×
584	return FPGA_EXCEPTION;	×
585	}
586	return FPGA_OK;	×
587	out:	×
588	opae_mutex_unlock(res, &fpga_perf->lock);	×
589	return FPGA_EXCEPTION;	×
590	}
591
592	fpga_result fpgaPerfCounterStopRecord(fpga_perf_counter *fpga_perf)	×
593	{
594	char buf[DFL_PERF_STR_MAX] = { 0 };	×
595	uint64_t loop = 0;	×
596	uint64_t inner_loop = 0;	×
597	int res = 0;	×
598	struct read_format rdft = (struct read_format ) buf;	×
599
600	if (!fpga_perf) {	×
601	OPAE_ERR("Invalid input parameters");	×
602	return FPGA_INVALID_PARAM;	×
603	}
604
605	if (fpga_perf_check_and_lock(fpga_perf)) {	×
606	OPAE_ERR("Failed to lock perf mutex");	×
607	return FPGA_EXCEPTION;	×
608	}
609	if (ioctl(fpga_perf->perf_events[0].fd, PERF_EVENT_IOC_DISABLE,	×
610	PERF_IOC_FLAG_GROUP) == -1) {
611	OPAE_ERR("PERF_EVENT_IOC_ENABLE ioctl failed: %s",	×
612	strerror(errno));
613	goto out;	×
614	}
615	if (read(fpga_perf->perf_events[0].fd, rdft, sizeof(buf)) == -1) {	×
616	OPAE_ERR("read fpga perf counter failed");	×
617	goto out;	×
618	}
619	for (loop = 0; loop < (uint64_t)rdft->nr; loop++) {	×
620	for (inner_loop = 0; inner_loop < fpga_perf->num_perf_events;	×
621	inner_loop++) {	×
622	if (rdft->values[loop].id == fpga_perf->perf_events[inner_loop].id)	×
623	fpga_perf->perf_events[inner_loop].stop_value = rdft->values[loop].value;	×
624	}
625	}
626	if (opae_mutex_unlock(res, &fpga_perf->lock)) {	×
627	OPAE_ERR("Failed to unlock perf mutex");	×
628	return FPGA_EXCEPTION;	×
629	}
630	return FPGA_OK;	×
631	out:	×
632	opae_mutex_unlock(res, &fpga_perf->lock);	×
633	return FPGA_EXCEPTION;	×
634	}
635
636	fpga_result fpgaPerfCounterPrint(FILE f, fpga_perf_counter fpga_perf)	×
637	{
638	uint64_t loop = 0;	×
639	int res = 0;	×
640
641	if (!fpga_perf \|\| !f) {	×
642	OPAE_ERR("Invalid input parameters");	×
643	return FPGA_INVALID_PARAM;	×
644	}
645
646	if (fpga_perf_check_and_lock(fpga_perf)) {	×
647	OPAE_ERR("Failed to lock perf mutex");	×
648	return FPGA_EXCEPTION;	×
649	}
650
651	fprintf(f, "\n");	×
652	for (loop = 0; loop < fpga_perf->num_perf_events; loop++)	×
653	fprintf(f, "%s\t", fpga_perf->perf_events[loop].event_name);	×
654
655	fprintf(f, "\n");	×
656	for (loop = 0; loop < fpga_perf->num_perf_events; loop++) {	×
657	if (!fpga_perf->perf_events[loop].config)	×
658	continue;	×
659	fprintf(f, "%ld\t\t", (fpga_perf->perf_events[loop].stop_value	×
660	- fpga_perf->perf_events[loop].start_value));	×
661	}
662
663	fprintf(f, "\n");	×
664
665	if (opae_mutex_unlock(res, &fpga_perf->lock)) {	×
666	OPAE_ERR("Failed to unlock perf mutex");	×
667	return FPGA_EXCEPTION;	×
668	}
669
670	return FPGA_OK;	×
671	}
672
673	fpga_result fpgaPerfCounterDestroy(fpga_perf_counter *fpga_perf)	×
674	{
675	int res = 0;	×
676
677	if (!fpga_perf) {	×
678	OPAE_ERR("Invalid input parameters");	×
679	return FPGA_INVALID_PARAM;	×
680	}
681	if (fpga_perf_check_and_lock(fpga_perf)) {	×
682	OPAE_ERR("Failed to lock perf mutex");	×
683	return FPGA_EXCEPTION;	×
684	}
685	if (fpga_perf->format_type) {	×
686	free(fpga_perf->format_type);	×
687	fpga_perf->format_type = NULL;	×
688	}
689	if (fpga_perf->perf_events) {	×
690	free(fpga_perf->perf_events);	×
691	fpga_perf->perf_events = NULL;	×
692	}
693
694	if (opae_mutex_unlock(res, &fpga_perf->lock)) {	×
695	OPAE_ERR("Failed to unlock perf mutex");	×
696	return FPGA_EXCEPTION;	×
697	}
698	if (fpga_perf_mutex_destroy(fpga_perf) != FPGA_OK) {	×
699	OPAE_ERR("Failed to destroy the mutex");	×
700	return FPGA_EXCEPTION;	×
701	}
702
703	return FPGA_OK;	×
704	}

OPAE / opae-sdk / 1448838130

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