1215292813

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github

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Pull Request Pull Request #2218: Tools: fix fpgainfo mac command to prints mac count and address list.

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59.64

/tools/libboard/board_n6010/board_n6010.c

// Copyright(c) 2021, Intel Corporation
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.

#ifdef HAVE_CONFIG_H
#include <config.h>
#endif // HAVE_CONFIG_H

#include <glob.h>
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <regex.h>
#include <opae/properties.h>
#include <opae/utils.h>
#include <opae/fpga.h>
#include <netinet/ether.h>
#include <net/ethernet.h>
#include <opae/uio.h>
#include "../board_common/board_common.h"
#include "board_n6010.h"

#define FPGA_VAR_BUF_LEN       256
#define MAC_BUF_LEN            19
#define UNUSED_PARAM(x) ((void)x)
#define FEATURE_DEV "/sys/bus/pci/devices/*%x*:*%x*:*%x*.*%x*/fpga_region"\
                                        "/region*/dfl-fme*/dfl_dev*"
// DFL SYSFS
#define DFL_SYSFS_BMCFW_VER                     "dfl*/bmcfw_version"
#define DFL_SYSFS_MAX10_VER                     "dfl*/bmc_version"

#define DFL_SYSFS_MACADDR_PATH                  "dfl*/mac_address"
#define DFL_SYSFS_MACCNT_PATH                   "dfl*/mac_count"

#define DFL_SEC_PMCI_GLOB "*dfl*/**/security/"
#define DFL_SEC_USER_FLASH_COUNT  DFL_SEC_PMCI_GLOB "*flash_count"
#define DFL_SEC_BMC_CANCEL        DFL_SEC_PMCI_GLOB "bmc_canceled_csks"
#define DFL_SEC_BMC_ROOT          DFL_SEC_PMCI_GLOB "bmc_root_entry_hash"
#define DFL_SEC_PR_CANCEL         DFL_SEC_PMCI_GLOB "pr_canceled_csks"
#define DFL_SEC_PR_ROOT           DFL_SEC_PMCI_GLOB "pr_root_entry_hash"
#define DFL_SEC_SR_CANCEL         DFL_SEC_PMCI_GLOB "sr_canceled_csks"
#define DFL_SEC_SR_ROOT           DFL_SEC_PMCI_GLOB "sr_root_entry_hash"


#define HSSI_FEATURE_ID                  0x15
#define HSSI_100G_PROFILE                       27
#define HSSI_25G_PROFILE                        21
#define HSSI_10_PROFILE                         20

#define HSSI_FEATURE_LIST                       0xC
#define HSSI_PORT_ATTRIBUTE                     0x10
#define HSSI_VERSION                            0x8

// boot page info sysfs
#define DFL_SYSFS_BOOT_GLOB "*dfl*/**/fpga_boot_image"
#define BOOTPAGE_PATTERN "_([0-9a-zA-Z]+)"

// image info sysfs
#define DFL_SYSFS_IMAGE_INFO_GLOB "*dfl*/**/fpga_image_directory"
#define IMAGE_INFO_STRIDE 4096
#define IMAGE_INFO_SIZE     32
#define IMAGE_INFO_COUNT     3

// hssi version
struct hssi_version {
        union {
                uint32_t csr;
                struct {
                        uint32_t rsvd : 8;
                        uint32_t minor : 8;
                        uint32_t major : 16;
                };
        };
};

// hssi feature list CSR
struct hssi_feature_list {
        union {
                uint32_t csr;
                struct {
                        uint32_t axi4_support : 1;
                        uint32_t hssi_num : 4;
                        uint32_t reserved : 27;
                };
        };
};

// hssi port attribute CSR
//Interface Attribute Port X Parameters, X =0-15
//Byte Offset: 0x10 + X * 4
struct hssi_port_attribute {
        union {
                uint32_t csr;
                struct {
                        uint32_t profile : 6;
                        uint32_t ready_latency : 4;
                        uint32_t data_bus_width : 3;
                        uint32_t low_speed_mac : 1;
                        uint32_t dynamic_pr : 1;
                        uint32_t reserved : 16;
                };
        };
};

typedef struct hssi_port_profile {

        uint32_t port_index;
        char profile[FPGA_VAR_BUF_LEN];

} hssi_port_profile;

#define HSS_PORT_PROFILE_SIZE 33

hssi_port_profile hssi_port_profiles[] = {

        {.port_index = 0, .profile = "LL100G"},
        {.port_index = 1, .profile = "Ultra100G"},
        {.port_index = 2, .profile = "LL50G"},
        {.port_index = 3, .profile = "LL40G"},
        {.port_index = 4, .profile = "Ultra40G"},
        {.port_index = 5, .profile = "25_50G"},
        {.port_index = 6, .profile = "10_25G"},
        {.port_index = 7, .profile = "MRPHY"},
        {.port_index = 8, .profile = "LL10G"},
        {.port_index = 9, .profile = "TSE PCS"},
        {.port_index = 10, .profile = "TSE MAC"},
        {.port_index = 11, .profile = "Flex-E"},
        {.port_index = 12, .profile = "OTN"},
        {.port_index = 13, .profile = "General PCS-Direct"},
        {.port_index = 14, .profile = "General FEC-Direct"},
        {.port_index = 15, .profile = "General PMA-Direct"},
        {.port_index = 16, .profile = "MII"},
        {.port_index = 17, .profile = "Ethernet PCS-Direct"},
        {.port_index = 18, .profile = "Ethernet FEC-Direct"},
        {.port_index = 19, .profile = "Ethernet PMA-Direct"},
        {.port_index = 20, .profile = "10GbE"},
        {.port_index = 21, .profile = "25GbE"},
        {.port_index = 22, .profile = "40GCAUI-4"},
        {.port_index = 23, .profile = "50GAUI-2"},
        {.port_index = 24, .profile = "50GAUI-1"},
        {.port_index = 25, .profile = "100GAUI-1"},
        {.port_index = 26, .profile = "100GAUI-2"},
        {.port_index = 27, .profile = "100GCAUI-4"},
        {.port_index = 28, .profile = "200GAUI-2"},
        {.port_index = 29, .profile = "200GAUI-4"},
        {.port_index = 30, .profile = "200GAUI-8"},
        {.port_index = 31, .profile = "400GAUI-4"},
        {.port_index = 32, .profile = "400GAUI-8"}
 };


// Parse firmware version
fpga_result parse_fw_ver(char *buf, char *fw_ver, size_t len)
{
        uint32_t  var = 0;
        fpga_result res = FPGA_OK;
        int retval = 0;
        char *endptr = NULL;

        if (buf == NULL || fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        /* BMC FW version format reading
        NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
        NIOS FW is up e.g. 1.0.1 for first release
        [31:24] 8hFF Firmware Support Revision - ASCII code
        0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
        */

        errno = 0;
        var = strtoul(buf, &endptr, 16);
        if (endptr != buf + strlen(buf)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }

        retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);
        if (retval < 0) {
                OPAE_ERR("error in formatting version");
                return FPGA_EXCEPTION;
        }

        return res;
}

// Read BMC firmware version
fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)
{
        fpga_result res = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN] = { 0 };

        if (bmcfw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, bmcfw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}


// Read MAX10 firmware version
fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)
{
        fpga_result res = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN] = { 0 };

        if (max10fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, max10fw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}

// print mac address
void print_mac_address(struct ether_addr *eth_addr, int count)
{
        char mac_str[18] = { 0 };

        if (eth_addr == NULL || count <= 0)
                return;

        printf("%s %-20d : %s \n", "MAC address", 0,
                ether_ntoa_r(eth_addr, mac_str));
        for (int i = 1; i < count; ++i) {
                // increment mac address
                for (int j = 5; j >= 0; j--) {
                        if (eth_addr->ether_addr_octet[j] == 0xff) {
                                continue;
                        } else {
                                eth_addr->ether_addr_octet[j]++;
                                break;
                        }
                }

                if ((eth_addr->ether_addr_octet[0] == 0xff) &&
                        (eth_addr->ether_addr_octet[1] == 0xff) &&
                        (eth_addr->ether_addr_octet[2] == 0xff) &&
                        (eth_addr->ether_addr_octet[3] == 0xff) &&
                        (eth_addr->ether_addr_octet[4] == 0xff) &&
                        (eth_addr->ether_addr_octet[5] == 0xff)) {
                        printf("%s %-20d : %s \n", "MAC address", i, "N/A");
                        continue;
                }
                printf("%s %-20d : %s \n", "MAC address", i,
                        ether_ntoa_r(eth_addr, mac_str));

        }
}

// print mac information
fpga_result print_mac_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        char buf[MAC_BUF_LEN] = { 0 };
        char count[MAC_BUF_LEN] = { 0 };
        int n = 0;
        char *endptr = NULL;
        struct ether_addr mac_addr ;
        memset(&mac_addr, 0, sizeof(mac_addr));

        res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, (char *)buf, MAC_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read mac information");
                return res;
        }

        ether_aton_r(buf, &mac_addr);

        res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, (char *)count, MAC_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read mac information");
                return res;
        }

        errno = 0;
        n = strtol(count, &endptr, 10);
        if (endptr != count + strlen(count)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }
        printf("%-32s : %d\n", "Number of MACs", n);

        if (n < 0 || n > 0xFFFF) {
                OPAE_ERR("Invalid mac count");
                return FPGA_EXCEPTION;
        }

        if ((mac_addr.ether_addr_octet[0] == 0xff) &&
                (mac_addr.ether_addr_octet[1] == 0xff) &&
                (mac_addr.ether_addr_octet[2] == 0xff) &&
                (mac_addr.ether_addr_octet[3] == 0xff) &&
                (mac_addr.ether_addr_octet[4] == 0xff) &&
                (mac_addr.ether_addr_octet[5] == 0xff)) {
                OPAE_ERR("Invalid MAC address");
                return FPGA_EXCEPTION;
        }

        print_mac_address(&mac_addr, n);

        return res;
}



// print board information
fpga_result print_board_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        fpga_result resval = FPGA_OK;
        char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };
        char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };

        res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read bmc version");
                resval = res;
        }

        res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read max10 version");
                resval = res;
        }

        printf("FPGA SmartNIC N6010 Card \n");
        printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);
        printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);

        return resval;
}




// print phy group information
fpga_result print_phy_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        struct opae_uio uio;
        char feature_dev[SYSFS_MAX_SIZE] = { 0 };
        struct hssi_port_attribute port_profile;
        struct hssi_feature_list  feature_list;
        struct hssi_version  hssi_ver;
        uint8_t *mmap_ptr = NULL;
        uint32_t i = 0;

        res = find_dev_feature(token, HSSI_FEATURE_ID, feature_dev);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to find feature ");
                return res;
        }

        res = opae_uio_open(&uio, feature_dev);
        if (res) {
                OPAE_ERR("Failed to open uio");
                return res;
        }

        res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL);
        if (res) {
                OPAE_ERR("Failed to get uio region");
                opae_uio_close(&uio);
                return res;
        }

        feature_list.csr = *((uint32_t *) (mmap_ptr + HSSI_FEATURE_LIST));
        hssi_ver.csr = *((uint32_t *)(mmap_ptr + HSSI_VERSION));

        printf("//****** HSSI information ******//\n");
        printf("%-32s : %d.%d  \n", "HSSI version", hssi_ver.major, hssi_ver.minor);
        printf("%-32s : %d  \n", "Number of ports", feature_list.hssi_num);

        for (i = 0; i < feature_list.hssi_num; i++) {
                port_profile.csr = *((uint32_t *)(mmap_ptr +
                        HSSI_PORT_ATTRIBUTE + i * 4));

                if (port_profile.profile > HSS_PORT_PROFILE_SIZE) {
                        printf("Port%-28d :%s\n", i, "N/A");
                        continue;
                }

                for (int j = 0; j < HSS_PORT_PROFILE_SIZE; j++) {
                        if (hssi_port_profiles[j].port_index == port_profile.profile) {
                                printf("Port%-28d :%s\n", i, hssi_port_profiles[j].profile);
                                break;
                        }
                 }
        }

        opae_uio_close(&uio);
        return res;
}

// Sec info
fpga_result print_sec_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        fpga_result resval = FPGA_OK;
        fpga_object tcm_object;
        char name[SYSFS_PATH_MAX] = { 0 };

        res = fpgaTokenGetObject(token, DFL_SEC_PMCI_GLOB, &tcm_object,
                FPGA_OBJECT_GLOB);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get token Object");
                return res;
        }
        printf("********** SEC Info START ************ \n");

        // BMC Keys
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_BMC_ROOT, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("BMC root entry hash: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read TCM BMC root entry hash");
                printf("BMC root entry hash: %s\n", "None");
                resval = res;
        }

        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_BMC_CANCEL, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("BMC CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");
        } else {
                OPAE_MSG("Failed to Read BMC CSK IDs canceled");
                printf("BBMC CSK IDs canceled: %s\n", "None");
                resval = res;
        }

        // PR Keys
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_PR_ROOT, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("PR root entry hash: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read PR root entry hash");
                printf("PR root entry hash: %s\n", "None");
                resval = res;
        }

        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_PR_CANCEL, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("AFU/PR CSK IDs canceled: %s\n",
                        strlen(name) > 0 ? name : "None");
        } else {
                OPAE_MSG("Failed to Read AFU CSK/PR IDs canceled");
                printf("AFU/PR CSK IDs canceled: %s\n", "None");
                resval = res;
        }

        // SR Keys
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_SR_ROOT, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("FIM root entry hash: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read FIM root entry hash");
                printf("FIM root entry hash: %s\n", "None");
                resval = res;
        }

        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_SR_CANCEL, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("FIM CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");
        } else {
                OPAE_MSG("Failed to Read FIM CSK IDs canceled");
                printf("FIM CSK IDs canceled: %s\n", "None");
                resval = res;
        }

        // User flash count
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_USER_FLASH_COUNT, name,
                SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("User flash update counter: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read User flash update counter");
                printf("User flash update counter: %s\n", "None");
                resval = res;
        }

        res = fpgaDestroyObject(&tcm_object);
        if (res != FPGA_OK) {
                OPAE_MSG("Failed to Destroy Object");
                resval = res;
        }

        printf("********** SEC Info END ************ \n");

        return resval;
}

// print fme verbose info
fpga_result print_fme_verbose_info(fpga_token token)
{
        UNUSED_PARAM(token);
        return FPGA_OK;;
}

// prints fpga boot page info
fpga_result fpga_boot_info(fpga_token token)
{
        char boot[SYSFS_PATH_MAX] = { 0 };
        char page[SYSFS_PATH_MAX] = { 0 };
        fpga_result res           = FPGA_OK;
        int reg_res               = 0;
        char err[128]           = { 0 };
        regex_t re;
        regmatch_t matches[3];

        // boot page
        memset(boot, 0, sizeof(boot));
        res = read_sysfs(token, DFL_SYSFS_BOOT_GLOB, boot, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {

                reg_res = regcomp(&re, BOOTPAGE_PATTERN, REG_EXTENDED | REG_ICASE);
                if (reg_res) {
                        OPAE_ERR("Error compiling regex");
                        return FPGA_EXCEPTION;
                }

                reg_res = regexec(&re, boot, 3, matches, 0);
                if (reg_res) {
                        regerror(reg_res, &re, err, sizeof(err));
                        OPAE_MSG("Error executing regex: %s", err);
                        regfree(&re);
                        return FPGA_EXCEPTION;
                }
                memcpy(page, boot + matches[0].rm_so + 1,
                        matches[0].rm_eo - (matches[0].rm_so + 1));
                page[matches[0].rm_eo - (matches[0].rm_so + 1)] = '\0';

                printf("%-32s : %s\n", "Boot Page", page);
                regfree(&re);
        } else {
                OPAE_MSG("Failed to Read Boot Page");
                printf("%-32s : %s\n", "Boot Page", "N/A");
        }

        return res;
}

// prints fpga image info
fpga_result fpga_image_info(fpga_token token)
{
        const char *image_info_label[IMAGE_INFO_COUNT] = {
                "Factory Image Info",
                "User1 Image Info",
                "User2 Image Info",
        };
        fpga_object fpga_object;
        fpga_result res;
        size_t i;

        res = fpgaTokenGetObject(token, DFL_SYSFS_IMAGE_INFO_GLOB,
                        &fpga_object, FPGA_OBJECT_GLOB);
        if (res != FPGA_OK) {
                OPAE_MSG("Failed to get token Object");
                return res;
        }

        for (i = 0; i < IMAGE_INFO_COUNT; i++) {
                size_t offset = IMAGE_INFO_STRIDE * i;
                uint8_t data[IMAGE_INFO_SIZE + 1] = { 0 };
                char *image_info = (char *)data;
                size_t p;

                printf("%-32s : ", image_info_label[i]);

                res = fpgaObjectRead(fpga_object, data, offset,
                                IMAGE_INFO_SIZE, FPGA_OBJECT_RAW);
                if (res != FPGA_OK) {
                        printf("N/A\n");
                        continue;
                }

                for (p = 0; p < IMAGE_INFO_SIZE; p++)
                        if (data[p] != 0xff)
                                break;

                if (p >= IMAGE_INFO_SIZE) {
                        printf("None\n");
                        continue;
                }

                if (strlen(image_info) == 0) {
                        printf("Empty\n");
                        continue;
                }

                printf("%s\n", image_info);
        }

        if (fpgaDestroyObject(&fpga_object) != FPGA_OK)
                OPAE_ERR("Failed to Destroy Object");

        return res;
}

1	// Copyright(c) 2021, Intel Corporation
2	//
3	// Redistribution and use in source and binary forms, with or without
4	// modification, are permitted provided that the following conditions are met:
5	//
6	// * Redistributions of source code must retain the above copyright notice,
7	// this list of conditions and the following disclaimer.
8	// * Redistributions in binary form must reproduce the above copyright notice,
9	// this list of conditions and the following disclaimer in the documentation
10	// and/or other materials provided with the distribution.
11	// * Neither the name of Intel Corporation nor the names of its contributors
12	// may be used to endorse or promote products derived from this software
13	// without specific prior written permission.
14	//
15	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16	// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19	// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20	// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21	// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22	// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23	// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24	// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25	// POSSIBILITY OF SUCH DAMAGE.
26
27	#ifdef HAVE_CONFIG_H
28	#include <config.h>
29	#endif // HAVE_CONFIG_H
30
31	#include <glob.h>
32	#include <stdio.h>
33	#include <errno.h>
34	#include <string.h>
35	#include <regex.h>
36	#include <opae/properties.h>
37	#include <opae/utils.h>
38	#include <opae/fpga.h>
39	#include <netinet/ether.h>
40	#include <net/ethernet.h>
41	#include <opae/uio.h>
42	#include "../board_common/board_common.h"
43	#include "board_n6010.h"
44
45	#define FPGA_VAR_BUF_LEN 256
46	#define MAC_BUF_LEN 19
47	#define UNUSED_PARAM(x) ((void)x)
48	#define FEATURE_DEV "/sys/bus/pci/devices/%x:%x:%x.%x/fpga_region"\
49	"/region/dfl-fme/dfl_dev*"
50	// DFL SYSFS
51	#define DFL_SYSFS_BMCFW_VER "dfl*/bmcfw_version"
52	#define DFL_SYSFS_MAX10_VER "dfl*/bmc_version"
53
54	#define DFL_SYSFS_MACADDR_PATH "dfl*/mac_address"
55	#define DFL_SYSFS_MACCNT_PATH "dfl*/mac_count"
56
57	#define DFL_SEC_PMCI_GLOB "dfl/**/security/"
58	#define DFL_SEC_USER_FLASH_COUNT DFL_SEC_PMCI_GLOB "*flash_count"
59	#define DFL_SEC_BMC_CANCEL DFL_SEC_PMCI_GLOB "bmc_canceled_csks"
60	#define DFL_SEC_BMC_ROOT DFL_SEC_PMCI_GLOB "bmc_root_entry_hash"
61	#define DFL_SEC_PR_CANCEL DFL_SEC_PMCI_GLOB "pr_canceled_csks"
62	#define DFL_SEC_PR_ROOT DFL_SEC_PMCI_GLOB "pr_root_entry_hash"
63	#define DFL_SEC_SR_CANCEL DFL_SEC_PMCI_GLOB "sr_canceled_csks"
64	#define DFL_SEC_SR_ROOT DFL_SEC_PMCI_GLOB "sr_root_entry_hash"
65
66
67	#define HSSI_FEATURE_ID 0x15
68	#define HSSI_100G_PROFILE 27
69	#define HSSI_25G_PROFILE 21
70	#define HSSI_10_PROFILE 20
71
72	#define HSSI_FEATURE_LIST 0xC
73	#define HSSI_PORT_ATTRIBUTE 0x10
74	#define HSSI_VERSION 0x8
75
76	// boot page info sysfs
77	#define DFL_SYSFS_BOOT_GLOB "dfl/**/fpga_boot_image"
78	#define BOOTPAGE_PATTERN "_([0-9a-zA-Z]+)"
79
80	// image info sysfs
81	#define DFL_SYSFS_IMAGE_INFO_GLOB "dfl/**/fpga_image_directory"
82	#define IMAGE_INFO_STRIDE 4096
83	#define IMAGE_INFO_SIZE 32
84	#define IMAGE_INFO_COUNT 3
85
86	// hssi version
87	struct hssi_version {
88	union {
89	uint32_t csr;
90	struct {
91	uint32_t rsvd : 8;
92	uint32_t minor : 8;
93	uint32_t major : 16;
94	};
95	};
96	};
97
98	// hssi feature list CSR
99	struct hssi_feature_list {
100	union {
101	uint32_t csr;
102	struct {
103	uint32_t axi4_support : 1;
104	uint32_t hssi_num : 4;
105	uint32_t reserved : 27;
106	};
107	};
108	};
109
110	// hssi port attribute CSR
111	//Interface Attribute Port X Parameters, X =0-15
112	//Byte Offset: 0x10 + X * 4
113	struct hssi_port_attribute {
114	union {
115	uint32_t csr;
116	struct {
117	uint32_t profile : 6;
118	uint32_t ready_latency : 4;
119	uint32_t data_bus_width : 3;
120	uint32_t low_speed_mac : 1;
121	uint32_t dynamic_pr : 1;
122	uint32_t reserved : 16;
123	};
124	};
125	};
126
127	typedef struct hssi_port_profile {
128
129	uint32_t port_index;
130	char profile[FPGA_VAR_BUF_LEN];
131
132	} hssi_port_profile;
133
134	#define HSS_PORT_PROFILE_SIZE 33
135
136	hssi_port_profile hssi_port_profiles[] = {
137
138	{.port_index = 0, .profile = "LL100G"},
139	{.port_index = 1, .profile = "Ultra100G"},
140	{.port_index = 2, .profile = "LL50G"},
141	{.port_index = 3, .profile = "LL40G"},
142	{.port_index = 4, .profile = "Ultra40G"},
143	{.port_index = 5, .profile = "25_50G"},
144	{.port_index = 6, .profile = "10_25G"},
145	{.port_index = 7, .profile = "MRPHY"},
146	{.port_index = 8, .profile = "LL10G"},
147	{.port_index = 9, .profile = "TSE PCS"},
148	{.port_index = 10, .profile = "TSE MAC"},
149	{.port_index = 11, .profile = "Flex-E"},
150	{.port_index = 12, .profile = "OTN"},
151	{.port_index = 13, .profile = "General PCS-Direct"},
152	{.port_index = 14, .profile = "General FEC-Direct"},
153	{.port_index = 15, .profile = "General PMA-Direct"},
154	{.port_index = 16, .profile = "MII"},
155	{.port_index = 17, .profile = "Ethernet PCS-Direct"},
156	{.port_index = 18, .profile = "Ethernet FEC-Direct"},
157	{.port_index = 19, .profile = "Ethernet PMA-Direct"},
158	{.port_index = 20, .profile = "10GbE"},
159	{.port_index = 21, .profile = "25GbE"},
160	{.port_index = 22, .profile = "40GCAUI-4"},
161	{.port_index = 23, .profile = "50GAUI-2"},
162	{.port_index = 24, .profile = "50GAUI-1"},
163	{.port_index = 25, .profile = "100GAUI-1"},
164	{.port_index = 26, .profile = "100GAUI-2"},
165	{.port_index = 27, .profile = "100GCAUI-4"},
166	{.port_index = 28, .profile = "200GAUI-2"},
167	{.port_index = 29, .profile = "200GAUI-4"},
168	{.port_index = 30, .profile = "200GAUI-8"},
169	{.port_index = 31, .profile = "400GAUI-4"},
170	{.port_index = 32, .profile = "400GAUI-8"}
171	};
172
173
174	// Parse firmware version
175	fpga_result parse_fw_ver(char buf, char fw_ver, size_t len)	8✔
176	{
177	uint32_t var = 0;	8✔
178	fpga_result res = FPGA_OK;	8✔
179	int retval = 0;	8✔
180	char *endptr = NULL;	8✔
181
182	if (buf == NULL \|\| fw_ver == NULL) {	8✔
183	OPAE_ERR("Invalid Input parameters");	182✔
184	return FPGA_INVALID_PARAM;	2✔
185	}
186
187	/* BMC FW version format reading
188	NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
189	NIOS FW is up e.g. 1.0.1 for first release
190	[31:24] 8hFF Firmware Support Revision - ASCII code
191	0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
192	*/
193
194	errno = 0;	6✔
195	var = strtoul(buf, &endptr, 16);	6✔
196	if (endptr != buf + strlen(buf)) {	6✔
197	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	182✔
198	return FPGA_EXCEPTION;	2✔
199	}
200
201	retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);	4✔
202	if (retval < 0) {	4✔
203	OPAE_ERR("error in formatting version");	×
204	return FPGA_EXCEPTION;	×
205	}
206
207	return res;	4✔
208	}
209
210	// Read BMC firmware version
211	fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)	7✔
212	{
213	fpga_result res = FPGA_OK;	7✔
214	char buf[FPGA_VAR_BUF_LEN] = { 0 };	7✔
215
216	if (bmcfw_ver == NULL) {	7✔
217	OPAE_ERR("Invalid Input parameters");	91✔
218	return FPGA_INVALID_PARAM;	1✔
219	}
220
221	res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);	6✔
222	if (res != FPGA_OK) {	6✔
223	OPAE_ERR("Failed to get read object");	273✔
224	return res;	3✔
225	}
226
227	res = parse_fw_ver(buf, bmcfw_ver, len);	3✔
228	if (res != FPGA_OK) {	3✔
229	OPAE_ERR("Failed to parse version ");	91✔
230	}
231
232	return res;	3✔
233	}
234
235
236	// Read MAX10 firmware version
237	fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)	7✔
238	{
239	fpga_result res = FPGA_OK;	7✔
240	char buf[FPGA_VAR_BUF_LEN] = { 0 };	7✔
241
242	if (max10fw_ver == NULL) {	7✔
243	OPAE_ERR("Invalid Input parameters");	91✔
244	return FPGA_INVALID_PARAM;	1✔
245	}
246
247	res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);	6✔
248	if (res != FPGA_OK) {	6✔
249	OPAE_ERR("Failed to get read object");	273✔
250	return res;	3✔
251	}
252
253	res = parse_fw_ver(buf, max10fw_ver, len);	3✔
254	if (res != FPGA_OK) {	3✔
255	OPAE_ERR("Failed to parse version ");	91✔
256	}
257
258	return res;	3✔
259	}
260
261	// print mac address
262	void print_mac_address(struct ether_addr *eth_addr, int count)	9✔
263	{
264	char mac_str[18] = { 0 };	9✔
265
266	if (eth_addr == NULL \|\| count <= 0)	9✔
267	return;	×
268
269	printf("%s %-20d : %s \n", "MAC address", 0,	9✔
270	ether_ntoa_r(eth_addr, mac_str));
271	for (int i = 1; i < count; ++i) {	65✔
272	// increment mac address
273	for (int j = 5; j >= 0; j--) {	154✔
274	if (eth_addr->ether_addr_octet[j] == 0xff) {	153✔
275	continue;	98✔
276	} else {
277	eth_addr->ether_addr_octet[j]++;	55✔
278	break;	55✔
279	}
280	}
281
282	if ((eth_addr->ether_addr_octet[0] == 0xff) &&	56✔
283	(eth_addr->ether_addr_octet[1] == 0xff) &&	2✔
284	(eth_addr->ether_addr_octet[2] == 0xff) &&	2✔
285	(eth_addr->ether_addr_octet[3] == 0xff) &&	2✔
286	(eth_addr->ether_addr_octet[4] == 0xff) &&	2✔
287	(eth_addr->ether_addr_octet[5] == 0xff)) {	2✔
288	printf("%s %-20d : %s \n", "MAC address", i, "N/A");	2✔
289	continue;	2✔
290	}
291	printf("%s %-20d : %s \n", "MAC address", i,	54✔
292	ether_ntoa_r(eth_addr, mac_str));
293
294	}
295	}
296
297	// print mac information
298	fpga_result print_mac_info(fpga_token token)	11✔
299	{
300	fpga_result res = FPGA_OK;	11✔
301	char buf[MAC_BUF_LEN] = { 0 };	11✔
302	char count[MAC_BUF_LEN] = { 0 };	11✔
303	int n = 0;	11✔
304	char *endptr = NULL;	11✔
305	struct ether_addr mac_addr ;
306	memset(&mac_addr, 0, sizeof(mac_addr));	11✔
307
308	res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, (char *)buf, MAC_BUF_LEN - 1);	11✔
309	if (res != FPGA_OK) {	11✔
310	OPAE_ERR("Failed to read mac information");	91✔
311	return res;	1✔
312	}
313
314	ether_aton_r(buf, &mac_addr);	10✔
315
316	res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, (char *)count, MAC_BUF_LEN - 1);	10✔
317	if (res != FPGA_OK) {	10✔
318	OPAE_ERR("Failed to read mac information");	×
319	return res;	×
320	}
321
322	errno = 0;	10✔
323	n = strtol(count, &endptr, 10);	10✔
324	if (endptr != count + strlen(count)) {	10✔
325	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	×
326	return FPGA_EXCEPTION;	×
327	}
328	printf("%-32s : %d\n", "Number of MACs", n);	10✔
329
330	if (n < 0 \|\| n > 0xFFFF) {	10✔
331	OPAE_ERR("Invalid mac count");	×
332	return FPGA_EXCEPTION;	×
333	}
334
335	if ((mac_addr.ether_addr_octet[0] == 0xff) &&	10✔
336	(mac_addr.ether_addr_octet[1] == 0xff) &&	1✔
337	(mac_addr.ether_addr_octet[2] == 0xff) &&	1✔
338	(mac_addr.ether_addr_octet[3] == 0xff) &&	1✔
339	(mac_addr.ether_addr_octet[4] == 0xff) &&	1✔
340	(mac_addr.ether_addr_octet[5] == 0xff)) {	1✔
341	OPAE_ERR("Invalid MAC address");	91✔
342	return FPGA_EXCEPTION;	1✔
343	}
344
345	print_mac_address(&mac_addr, n);	9✔
346
347	return res;	9✔
348	}
349
350
351
352	// print board information
353	fpga_result print_board_info(fpga_token token)	2✔
354	{
355	fpga_result res = FPGA_OK;	2✔
356	fpga_result resval = FPGA_OK;	2✔
357	char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };	2✔
358	char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };	2✔
359
360	res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);	2✔
361	if (res != FPGA_OK) {	2✔
362	OPAE_ERR("Failed to read bmc version");	91✔
363	resval = res;	1✔
364	}
365
366	res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);	2✔
367	if (res != FPGA_OK) {	2✔
368	OPAE_ERR("Failed to read max10 version");	91✔
369	resval = res;	1✔
370	}
371
372	printf("FPGA SmartNIC N6010 Card \n");	2✔
373	printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);	2✔
374	printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);	2✔
375
376	return resval;	2✔
377	}
378
379
380
381
382	// print phy group information
383	fpga_result print_phy_info(fpga_token token)	4✔
384	{
385	fpga_result res = FPGA_OK;	4✔
386	struct opae_uio uio;
387	char feature_dev[SYSFS_MAX_SIZE] = { 0 };	4✔
388	struct hssi_port_attribute port_profile;
389	struct hssi_feature_list feature_list;
390	struct hssi_version hssi_ver;
391	uint8_t *mmap_ptr = NULL;	4✔
392	uint32_t i = 0;	4✔
393
394	res = find_dev_feature(token, HSSI_FEATURE_ID, feature_dev);	4✔
395	if (res != FPGA_OK) {	4✔
396	OPAE_ERR("Failed to find feature ");	182✔
397	return res;	2✔
398	}
399
400	res = opae_uio_open(&uio, feature_dev);	2✔
401	if (res) {	2✔
402	OPAE_ERR("Failed to open uio");	182✔
403	return res;	2✔
404	}
405
406	res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL);	×
407	if (res) {	×
408	OPAE_ERR("Failed to get uio region");	×
409	opae_uio_close(&uio);	×
410	return res;	×
411	}
412
413	feature_list.csr = ((uint32_t ) (mmap_ptr + HSSI_FEATURE_LIST));	×
414	hssi_ver.csr = ((uint32_t )(mmap_ptr + HSSI_VERSION));	×
415
416	printf("//**** HSSI information ****//\n");	×
417	printf("%-32s : %d.%d \n", "HSSI version", hssi_ver.major, hssi_ver.minor);	×
418	printf("%-32s : %d \n", "Number of ports", feature_list.hssi_num);	×
419
420	for (i = 0; i < feature_list.hssi_num; i++) {	×
421	port_profile.csr = ((uint32_t )(mmap_ptr +	×
422	HSSI_PORT_ATTRIBUTE + i * 4));	×
423
424	if (port_profile.profile > HSS_PORT_PROFILE_SIZE) {	×
425	printf("Port%-28d :%s\n", i, "N/A");	×
426	continue;	×
427	}
428
429	for (int j = 0; j < HSS_PORT_PROFILE_SIZE; j++) {	×
430	if (hssi_port_profiles[j].port_index == port_profile.profile) {	×
431	printf("Port%-28d :%s\n", i, hssi_port_profiles[j].profile);	×
432	break;	×
433	}
434	}
435	}
436
437	opae_uio_close(&uio);	×
438	return res;	×
439	}
440
441	// Sec info
442	fpga_result print_sec_info(fpga_token token)	2✔
443	{
444	fpga_result res = FPGA_OK;	2✔
445	fpga_result resval = FPGA_OK;	2✔
446	fpga_object tcm_object;
447	char name[SYSFS_PATH_MAX] = { 0 };	2✔
448
449	res = fpgaTokenGetObject(token, DFL_SEC_PMCI_GLOB, &tcm_object,	2✔
450	FPGA_OBJECT_GLOB);
451	if (res != FPGA_OK) {	2✔
452	OPAE_ERR("Failed to get token Object");	91✔
453	return res;	1✔
454	}
455	printf("******** SEC Info START ********** \n");	1✔
456
457	// BMC Keys
458	memset(name, 0, sizeof(name));	1✔
459	res = read_sysfs(token, DFL_SEC_BMC_ROOT, name, SYSFS_PATH_MAX - 1);	1✔
460	if (res == FPGA_OK) {	1✔
461	printf("BMC root entry hash: %s\n", name);	1✔
462	} else {
463	OPAE_MSG("Failed to Read TCM BMC root entry hash");	×
464	printf("BMC root entry hash: %s\n", "None");	×
465	resval = res;	×
466	}
467
468	memset(name, 0, sizeof(name));	1✔
469	res = read_sysfs(token, DFL_SEC_BMC_CANCEL, name, SYSFS_PATH_MAX - 1);	1✔
470	if (res == FPGA_OK) {	1✔
471	printf("BMC CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");	1✔
472	} else {
473	OPAE_MSG("Failed to Read BMC CSK IDs canceled");	×
474	printf("BBMC CSK IDs canceled: %s\n", "None");	×
475	resval = res;	×
476	}
477
478	// PR Keys
479	memset(name, 0, sizeof(name));	1✔
480	res = read_sysfs(token, DFL_SEC_PR_ROOT, name, SYSFS_PATH_MAX - 1);	1✔
481	if (res == FPGA_OK) {	1✔
482	printf("PR root entry hash: %s\n", name);	1✔
483	} else {
484	OPAE_MSG("Failed to Read PR root entry hash");	×
485	printf("PR root entry hash: %s\n", "None");	×
486	resval = res;	×
487	}
488
489	memset(name, 0, sizeof(name));	1✔
490	res = read_sysfs(token, DFL_SEC_PR_CANCEL, name, SYSFS_PATH_MAX - 1);	1✔
491	if (res == FPGA_OK) {	1✔
492	printf("AFU/PR CSK IDs canceled: %s\n",	1✔
493	strlen(name) > 0 ? name : "None");	1✔
494	} else {
495	OPAE_MSG("Failed to Read AFU CSK/PR IDs canceled");	×
496	printf("AFU/PR CSK IDs canceled: %s\n", "None");	×
497	resval = res;	×
498	}
499
500	// SR Keys
501	memset(name, 0, sizeof(name));	1✔
502	res = read_sysfs(token, DFL_SEC_SR_ROOT, name, SYSFS_PATH_MAX - 1);	1✔
503	if (res == FPGA_OK) {	1✔
504	printf("FIM root entry hash: %s\n", name);	1✔
505	} else {
506	OPAE_MSG("Failed to Read FIM root entry hash");	×
507	printf("FIM root entry hash: %s\n", "None");	×
508	resval = res;	×
509	}
510
511	memset(name, 0, sizeof(name));	1✔
512	res = read_sysfs(token, DFL_SEC_SR_CANCEL, name, SYSFS_PATH_MAX - 1);	1✔
513	if (res == FPGA_OK) {	1✔
514	printf("FIM CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");	1✔
515	} else {
516	OPAE_MSG("Failed to Read FIM CSK IDs canceled");	×
517	printf("FIM CSK IDs canceled: %s\n", "None");	×
518	resval = res;	×
519	}
520
521	// User flash count
522	memset(name, 0, sizeof(name));	1✔
523	res = read_sysfs(token, DFL_SEC_USER_FLASH_COUNT, name,	1✔
524	SYSFS_PATH_MAX - 1);
525	if (res == FPGA_OK) {	1✔
526	printf("User flash update counter: %s\n", name);	1✔
527	} else {
528	OPAE_MSG("Failed to Read User flash update counter");	×
529	printf("User flash update counter: %s\n", "None");	×
530	resval = res;	×
531	}
532
533	res = fpgaDestroyObject(&tcm_object);	1✔
534	if (res != FPGA_OK) {	1✔
535	OPAE_MSG("Failed to Destroy Object");	×
536	resval = res;	×
537	}
538
539	printf("******** SEC Info END ********** \n");	1✔
540
541	return resval;	1✔
542	}
543
544	// print fme verbose info
545	fpga_result print_fme_verbose_info(fpga_token token)	×
546	{
547	UNUSED_PARAM(token);
548	return FPGA_OK;;	×
549	}
550
551	// prints fpga boot page info
552	fpga_result fpga_boot_info(fpga_token token)	×
553	{
554	char boot[SYSFS_PATH_MAX] = { 0 };	×
555	char page[SYSFS_PATH_MAX] = { 0 };	×
556	fpga_result res = FPGA_OK;	×
557	int reg_res = 0;	×
558	char err[128] = { 0 };	×
559	regex_t re;
560	regmatch_t matches[3];
561
562	// boot page
563	memset(boot, 0, sizeof(boot));	×
564	res = read_sysfs(token, DFL_SYSFS_BOOT_GLOB, boot, SYSFS_PATH_MAX - 1);	×
565	if (res == FPGA_OK) {	×
566
567	reg_res = regcomp(&re, BOOTPAGE_PATTERN, REG_EXTENDED \| REG_ICASE);	×
568	if (reg_res) {	×
569	OPAE_ERR("Error compiling regex");	×
570	return FPGA_EXCEPTION;	×
571	}
572
573	reg_res = regexec(&re, boot, 3, matches, 0);	×
574	if (reg_res) {	×
575	regerror(reg_res, &re, err, sizeof(err));	×
576	OPAE_MSG("Error executing regex: %s", err);	×
577	regfree(&re);	×
578	return FPGA_EXCEPTION;	×
579	}
580	memcpy(page, boot + matches[0].rm_so + 1,	×
581	matches[0].rm_eo - (matches[0].rm_so + 1));	×
582	page[matches[0].rm_eo - (matches[0].rm_so + 1)] = '\0';	×
583
584	printf("%-32s : %s\n", "Boot Page", page);	×
585	regfree(&re);	×
586	} else {
587	OPAE_MSG("Failed to Read Boot Page");	×
588	printf("%-32s : %s\n", "Boot Page", "N/A");	×
589	}
590
591	return res;	×
592	}
593
594	// prints fpga image info
595	fpga_result fpga_image_info(fpga_token token)	×
596	{
597	const char *image_info_label[IMAGE_INFO_COUNT] = {	×
598	"Factory Image Info",
599	"User1 Image Info",
600	"User2 Image Info",
601	};
602	fpga_object fpga_object;
603	fpga_result res;
604	size_t i;
605
606	res = fpgaTokenGetObject(token, DFL_SYSFS_IMAGE_INFO_GLOB,	×
607	&fpga_object, FPGA_OBJECT_GLOB);
608	if (res != FPGA_OK) {	×
609	OPAE_MSG("Failed to get token Object");	×
610	return res;	×
611	}
612
613	for (i = 0; i < IMAGE_INFO_COUNT; i++) {	×
614	size_t offset = IMAGE_INFO_STRIDE * i;	×
615	uint8_t data[IMAGE_INFO_SIZE + 1] = { 0 };	×
616	char image_info = (char )data;	×
617	size_t p;
618
619	printf("%-32s : ", image_info_label[i]);	×
620
621	res = fpgaObjectRead(fpga_object, data, offset,	×
622	IMAGE_INFO_SIZE, FPGA_OBJECT_RAW);
623	if (res != FPGA_OK) {	×
624	printf("N/A\n");	×
625	continue;	×
626	}
627
628	for (p = 0; p < IMAGE_INFO_SIZE; p++)	×
629	if (data[p] != 0xff)	×
630	break;	×
631
632	if (p >= IMAGE_INFO_SIZE) {	×
633	printf("None\n");	×
634	continue;	×
635	}
636
637	if (strlen(image_info) == 0) {	×
638	printf("Empty\n");	×
639	continue;	×
640	}
641
642	printf("%s\n", image_info);	×
643	}
644
645	if (fpgaDestroyObject(&fpga_object) != FPGA_OK)	×
646	OPAE_ERR("Failed to Destroy Object");	×
647
648	return res;	×
649	}

OPAE / opae-sdk / 1215292813

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