1124997467

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github

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<a href="https://github.com/OPAE/opae-sdk/commit/<a class=hub.com/OPAE/opae-sdk/commit/58cca95424b298de32b71ecc7e9bfa77a7c9dc91">58cca9542<a href="https://github.com/OPAE/opae-sdk/commit/58cca95424b298de32b71ecc7e9bfa77a7c9dc91">">Merge </a><a class="double-link" href="https://github.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://github.com/OPAE/opae-sdk/commit/c909706023238dfd0642e788326ca96437535eeb">c90970602</a>">c90970602</a><a href="https://github.com/OPAE/opae-sdk/commit/58cca95424b298de32b71ecc7e9bfa77a7c9dc91"> into 55c2ba16b">55c2ba16b</a>

Pull Request Pull Request #2158: Tools: Move fpgainfo boot page info to board specific modules

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/tools/libboard/board_n5010/board_n5010.c

// Original work Copyright(c) 2019-2020, Intel Corporation
// Modifications Copyright(c) 2021, Silicom Denmark A/S
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.

#ifdef HAVE_CONFIG_H
#include <config.h>
#endif // HAVE_CONFIG_H

#include <glob.h>
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <net/ethernet.h>
#include <opae/properties.h>
#include <opae/utils.h>
#include <opae/fpga.h>
#include <sys/ioctl.h>
#include <netinet/ether.h>

#include "board_n5010.h"
#include "../board_common/board_common.h"

#define MACADDR_LEN 19

// DFL SYSFS
#define DFL_SYSFS_BMCFW_VER                     "dfl*/**/spi_master/spi*/spi*/bmcfw_version"
#define DFL_SYSFS_MAX10_VER                     "dfl*/**/spi_master/spi*/spi*/bmc_version"

#define DFL_SYSFS_MACADDR_PATH                  "dfl*/**/spi_master/spi*/spi*.*/mac_address"
#define DFL_SYSFS_MACCNT_PATH                   "dfl*/**/spi_master/spi*/spi*.*/mac_count"


// Read BMC firmware version
fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)
{
        fpga_result res                = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN]     = { 0 };

        if (bmcfw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, bmcfw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}

fpga_result parse_fw_ver(char *buf, char *fw_ver, size_t len)
{
        uint32_t  var              = 0;
        fpga_result res            = FPGA_OK;
        int retval                 = 0;
        char *endptr               = NULL;

        if (buf == NULL || fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        /* BMC FW version format reading
        NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
        NIOS FW is up e.g. 1.0.1 for first release
        [31:24] 8hFF Firmware Support Revision - ASCII code
        0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
        */

        errno = 0;
        var = strtoul(buf, &endptr, 16);
        if (endptr != buf + strlen(buf)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }

        retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);
        if (retval < 0) {
                        OPAE_ERR("error in formatting version");
                        return FPGA_EXCEPTION;
        }

        return res;
}

// Read MAX10 firmware version
fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)
{
        fpga_result res = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN] = { 0 };

        if (max10fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, max10fw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}


// Read mac information
fpga_result read_mac_info(fpga_token token, uint32_t afu_channel_num,
                                                struct ether_addr *mac_addr)
{
        fpga_result res                = FPGA_OK;
        char mac_buf[MACADDR_LEN]      = { 0 };
        char mac_count[MACADDR_LEN]    = { 0 };
        uint64_t count                 = 0;
        char *endptr                   = NULL;

        if (mac_addr == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, mac_buf, MACADDR_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        ether_aton_r(mac_buf, mac_addr);

        res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, mac_count, MACADDR_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        errno = 0;
        count = strtoul(mac_count, &endptr, 16);
        if (endptr != mac_count + strlen(mac_count)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }

        if (afu_channel_num >= count) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        if ((mac_addr->ether_addr_octet[0] == 0xff) &&
                (mac_addr->ether_addr_octet[1] == 0xff) &&
                (mac_addr->ether_addr_octet[2] == 0xff) &&
                (mac_addr->ether_addr_octet[3] == 0xff) &&
                (mac_addr->ether_addr_octet[4] == 0xff) &&
                (mac_addr->ether_addr_octet[5] == 0xff)) {
                OPAE_ERR("Invalid MAC address");
                return FPGA_INVALID_PARAM;
        }

        mac_addr->ether_addr_octet[5] += afu_channel_num;

        return res;
}

// print board information
fpga_result print_board_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        fpga_result resval = FPGA_OK;
        char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };
        char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };

        res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read bmc version");
                resval = res;
        }

        res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read max10 version");
                resval = res;
        }

        printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);
        printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);

        return resval;
}

// print board information
fpga_result print_sec_info(fpga_token token)
{
        return print_sec_common_info(token);
}

// print mac information
fpga_result print_mac_info(fpga_token token)
{
        char mac_str[18] = { 0 };
        struct ether_addr MAC;
        fpga_result res = FPGA_OK;

        memset((void *)&MAC, 0, sizeof(MAC));

        res = read_mac_info(token, 0, &MAC);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read mac address");
        } else {
                printf("%-1s : %s\n", "MAC address",
                        ether_ntoa_r(&MAC, mac_str));
        }

        return res;
}

// print phy group information
fpga_result print_phy_info(fpga_token token)
{
        fpga_result res           = FPGA_OK;

        res = print_eth_interface_info(token, "n5010");
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read phy info");
                return res;
        }

        return res;
}

// prints fpga boot page info
fpga_result fpga_boot_info(fpga_token token)
{
        return print_common_boot_info(token);
}

1	// Original work Copyright(c) 2019-2020, Intel Corporation
2	// Modifications Copyright(c) 2021, Silicom Denmark A/S
3	//
4	// Redistribution and use in source and binary forms, with or without
5	// modification, are permitted provided that the following conditions are met:
6	//
7	// * Redistributions of source code must retain the above copyright notice,
8	// this list of conditions and the following disclaimer.
9	// * Redistributions in binary form must reproduce the above copyright notice,
10	// this list of conditions and the following disclaimer in the documentation
11	// and/or other materials provided with the distribution.
12	// * Neither the name of Intel Corporation nor the names of its contributors
13	// may be used to endorse or promote products derived from this software
14	// without specific prior written permission.
15	//
16	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17	// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20	// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21	// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22	// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23	// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24	// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25	// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26	// POSSIBILITY OF SUCH DAMAGE.
27
28	#ifdef HAVE_CONFIG_H
29	#include <config.h>
30	#endif // HAVE_CONFIG_H
31
32	#include <glob.h>
33	#include <stdio.h>
34	#include <errno.h>
35	#include <string.h>
36	#include <unistd.h>
37	#include <fcntl.h>
38	#include <sys/types.h>
39	#include <sys/stat.h>
40	#include <net/ethernet.h>
41	#include <opae/properties.h>
42	#include <opae/utils.h>
43	#include <opae/fpga.h>
44	#include <sys/ioctl.h>
45	#include <netinet/ether.h>
46
47	#include "board_n5010.h"
48	#include "../board_common/board_common.h"
49
50	#define MACADDR_LEN 19
51
52	// DFL SYSFS
53	#define DFL_SYSFS_BMCFW_VER "dfl//spi_master/spi/spi*/bmcfw_version"
54	#define DFL_SYSFS_MAX10_VER "dfl//spi_master/spi/spi*/bmc_version"
55
56	#define DFL_SYSFS_MACADDR_PATH "dfl//spi_master/spi/spi./mac_address"
57	#define DFL_SYSFS_MACCNT_PATH "dfl//spi_master/spi/spi./mac_count"
58
59
60	// Read BMC firmware version
61	fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)	2✔
62	{
63	fpga_result res = FPGA_OK;	2✔
64	char buf[FPGA_VAR_BUF_LEN] = { 0 };	2✔
65
66	if (bmcfw_ver == NULL) {	2✔
67	OPAE_ERR("Invalid Input parameters");	×
68	return FPGA_INVALID_PARAM;	×
69	}
70
71	res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);	2✔
72	if (res != FPGA_OK) {	2✔
73	OPAE_ERR("Failed to get read object");	182✔
74	return res;	2✔
75	}
76
77	res = parse_fw_ver(buf, bmcfw_ver, len);	×
78	if (res != FPGA_OK) {	×
79	OPAE_ERR("Failed to parse version ");	×
80	}
81
82	return res;	×
83	}
84
85	fpga_result parse_fw_ver(char buf, char fw_ver, size_t len)	×
86	{
87	uint32_t var = 0;	×
88	fpga_result res = FPGA_OK;	×
89	int retval = 0;	×
90	char *endptr = NULL;	×
91
92	if (buf == NULL \|\| fw_ver == NULL) {	×
93	OPAE_ERR("Invalid Input parameters");	×
94	return FPGA_INVALID_PARAM;	×
95	}
96
97	/* BMC FW version format reading
98	NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
99	NIOS FW is up e.g. 1.0.1 for first release
100	[31:24] 8hFF Firmware Support Revision - ASCII code
101	0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
102	*/
103
104	errno = 0;	×
105	var = strtoul(buf, &endptr, 16);	×
106	if (endptr != buf + strlen(buf)) {	×
107	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	×
108	return FPGA_EXCEPTION;	×
109	}
110
111	retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);	×
112	if (retval < 0) {	×
113	OPAE_ERR("error in formatting version");	×
114	return FPGA_EXCEPTION;	×
115	}
116
117	return res;	×
118	}
119
120	// Read MAX10 firmware version
121	fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)	2✔
122	{
123	fpga_result res = FPGA_OK;	2✔
124	char buf[FPGA_VAR_BUF_LEN] = { 0 };	2✔
125
126	if (max10fw_ver == NULL) {	2✔
127	OPAE_ERR("Invalid Input parameters");	×
128	return FPGA_INVALID_PARAM;	×
129	}
130
131	res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);	2✔
132	if (res != FPGA_OK) {	2✔
133	OPAE_ERR("Failed to get read object");	182✔
134	return res;	2✔
135	}
136
137	res = parse_fw_ver(buf, max10fw_ver, len);	×
138	if (res != FPGA_OK) {	×
139	OPAE_ERR("Failed to parse version ");	×
140	}
141
142	return res;	×
143	}
144
145
146	// Read mac information
147	fpga_result read_mac_info(fpga_token token, uint32_t afu_channel_num,	1✔
148	struct ether_addr *mac_addr)
149	{
150	fpga_result res = FPGA_OK;	1✔
151	char mac_buf[MACADDR_LEN] = { 0 };	1✔
152	char mac_count[MACADDR_LEN] = { 0 };	1✔
153	uint64_t count = 0;	1✔
154	char *endptr = NULL;	1✔
155
156	if (mac_addr == NULL) {	1✔
157	OPAE_ERR("Invalid Input parameters");	×
158	return FPGA_INVALID_PARAM;	×
159	}
160
161	res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, mac_buf, MACADDR_LEN - 1);	1✔
162	if (res != FPGA_OK) {	1✔
163	OPAE_ERR("Failed to get read object");	91✔
164	return res;	1✔
165	}
166
167	ether_aton_r(mac_buf, mac_addr);	×
168
169	res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, mac_count, MACADDR_LEN - 1);	×
170	if (res != FPGA_OK) {	×
171	OPAE_ERR("Failed to get read object");	×
172	return res;	×
173	}
174
175	errno = 0;	×
176	count = strtoul(mac_count, &endptr, 16);	×
177	if (endptr != mac_count + strlen(mac_count)) {	×
178	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	×
179	return FPGA_EXCEPTION;	×
180	}
181
182	if (afu_channel_num >= count) {	×
183	OPAE_ERR("Invalid Input parameters");	×
184	return FPGA_INVALID_PARAM;	×
185	}
186
187	if ((mac_addr->ether_addr_octet[0] == 0xff) &&	×
188	(mac_addr->ether_addr_octet[1] == 0xff) &&	×
189	(mac_addr->ether_addr_octet[2] == 0xff) &&	×
190	(mac_addr->ether_addr_octet[3] == 0xff) &&	×
191	(mac_addr->ether_addr_octet[4] == 0xff) &&	×
192	(mac_addr->ether_addr_octet[5] == 0xff)) {	×
193	OPAE_ERR("Invalid MAC address");	×
194	return FPGA_INVALID_PARAM;	×
195	}
196
197	mac_addr->ether_addr_octet[5] += afu_channel_num;	×
198
199	return res;	×
200	}
201
202	// print board information
203	fpga_result print_board_info(fpga_token token)	1✔
204	{
205	fpga_result res = FPGA_OK;	1✔
206	fpga_result resval = FPGA_OK;	1✔
207	char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };	1✔
208	char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };	1✔
209
210	res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);	1✔
211	if (res != FPGA_OK) {	1✔
212	OPAE_ERR("Failed to read bmc version");	91✔
213	resval = res;	1✔
214	}
215
216	res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);	1✔
217	if (res != FPGA_OK) {	1✔
218	OPAE_ERR("Failed to read max10 version");	91✔
219	resval = res;	1✔
220	}
221
222	printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);	1✔
223	printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);	1✔
224
225	return resval;	1✔
226	}
227
228	// print board information
229	fpga_result print_sec_info(fpga_token token)	1✔
230	{
231	return print_sec_common_info(token);	1✔
232	}
233
234	// print mac information
235	fpga_result print_mac_info(fpga_token token)	1✔
236	{
237	char mac_str[18] = { 0 };	1✔
238	struct ether_addr MAC;
239	fpga_result res = FPGA_OK;	1✔
240
241	memset((void *)&MAC, 0, sizeof(MAC));	1✔
242
243	res = read_mac_info(token, 0, &MAC);	1✔
244	if (res != FPGA_OK) {	1✔
245	OPAE_ERR("Failed to read mac address");	91✔
246	} else {
247	printf("%-1s : %s\n", "MAC address",	×
248	ether_ntoa_r(&MAC, mac_str));
249	}
250
251	return res;	1✔
252	}
253
254	// print phy group information
255	fpga_result print_phy_info(fpga_token token)	×
256	{
257	fpga_result res = FPGA_OK;	×
258
259	res = print_eth_interface_info(token, "n5010");	×
260	if (res != FPGA_OK) {	×
261	OPAE_ERR("Failed to read phy info");	×
262	return res;	×
263	}
264
265	return res;	×
266	}
267
268	// prints fpga boot page info
269	fpga_result fpga_boot_info(fpga_token token)	×
270	{
271	return print_common_boot_info(token);	×
272	}

OPAE / opae-sdk / 1124997467

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