1057057884

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github

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<a href="https://github.com/OPAE/opae-sdk/commit/<a class=hub.com/OPAE/opae-sdk/commit/b082d1b35cdf0b744cb9099fd48d04073056f255">b082d1b35<a href="https://github.com/OPAE/opae-sdk/commit/b082d1b35cdf0b744cb9099fd48d04073056f255">">Merge </a><a class="double-link" href="https://github.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://github.com/OPAE/opae-sdk/commit/f9aafc9490a37eea18ba2322b440393bf78a87bd">f9aafc949</a>">f9aafc949</a><a href="https://github.com/OPAE/opae-sdk/commit/b082d1b35cdf0b744cb9099fd48d04073056f255"> into 2a5d1419f">2a5d1419f</a>

Pull Request Pull Request #2131: tools: add security key support for n6010 smart NIC

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32.86

/tools/libboard/board_n6010/board_n6010.c

// Copyright(c) 2021, Intel Corporation
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.

#ifdef HAVE_CONFIG_H
#include <config.h>
#endif // HAVE_CONFIG_H

#include <glob.h>
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <opae/properties.h>
#include <opae/utils.h>
#include <opae/fpga.h>
#include <netinet/ether.h>
#include <opae/uio.h>
#include "../board_common/board_common.h"
#include "board_n6010.h"

#define FPGA_VAR_BUF_LEN       256
#define MACADDR_LEN            19
#define UNUSED_PARAM(x) ((void)x)
#define FEATURE_DEV "/sys/bus/pci/devices/*%x*:*%x*:*%x*.*%x*/fpga_region"\
                                        "/region*/dfl-fme*/dfl_dev*"
// DFL SYSFS
#define DFL_SYSFS_BMCFW_VER                     "dfl*/bmcfw_version"
#define DFL_SYSFS_MAX10_VER                     "dfl*/bmc_version"

#define DFL_SYSFS_MACADDR_PATH                  "dfl*/mac_address"
#define DFL_SYSFS_MACCNT_PATH                   "dfl*/mac_count"

#define DFL_SEC_PMCI_GLOB "*dfl*/**/security/"
#define DFL_SEC_USER_FLASH_COUNT  DFL_SEC_PMCI_GLOB "*flash_count"
#define DFL_SEC_BMC_CANCEL        DFL_SEC_PMCI_GLOB "bmc_canceled_csks"
#define DFL_SEC_BMC_ROOT          DFL_SEC_PMCI_GLOB "bmc_root_entry_hash"
#define DFL_SEC_PR_CANCEL         DFL_SEC_PMCI_GLOB "pr_canceled_csks"
#define DFL_SEC_PR_ROOT           DFL_SEC_PMCI_GLOB "pr_root_entry_hash"
#define DFL_SEC_SR_CANCEL         DFL_SEC_PMCI_GLOB "sr_canceled_csks"
#define DFL_SEC_SR_ROOT           DFL_SEC_PMCI_GLOB "sr_root_entry_hash"


#define HSSI_FEATURE_ID                  0x15
#define HSSI_100G_PROFILE                       27
#define HSSI_25G_PROFILE                        21
#define HSSI_10_PROFILE                         20

#define HSSI_FEATURE_LIST                       0xC
#define HSSI_PORT_ATTRIBUTE                     0x10
#define HSSI_VERSION                            0x8
// hssi version
struct hssi_version {
        union {
                uint32_t csr;
                struct {
                        uint32_t rsvd : 8;
                        uint32_t minor : 8;
                        uint32_t major : 16;
                };
        };
};

// hssi feature list CSR
struct hssi_feature_list {
        union {
                uint32_t csr;
                struct {
                        uint32_t axi4_support : 1;
                        uint32_t hssi_num : 4;
                        uint32_t reserved : 27;
                };
        };
};

// hssi port attribute CSR
//Interface Attribute Port X Parameters, X =0-15
//Byte Offset: 0x10 + X * 4
struct hssi_port_attribute {
        union {
                uint32_t csr;
                struct {
                        uint32_t profile : 6;
                        uint32_t ready_latency : 4;
                        uint32_t data_bus_width : 3;
                        uint32_t low_speed_mac : 1;
                        uint32_t dynamic_pr : 1;
                        uint32_t reserved : 16;
                };
        };
};

typedef struct hssi_port_profile {

        uint32_t port_index;
        char profile[FPGA_VAR_BUF_LEN];

} hssi_port_profile;

#define HSS_PORT_PROFILE_SIZE 33

hssi_port_profile hssi_port_profiles[] = {

        {.port_index = 0, .profile = "LL100G"},
        {.port_index = 1, .profile = "Ultra100G"},
        {.port_index = 2, .profile = "LL50G"},
        {.port_index = 3, .profile = "LL40G"},
        {.port_index = 4, .profile = "Ultra40G"},
        {.port_index = 5, .profile = "25_50G"},
        {.port_index = 6, .profile = "10_25G"},
        {.port_index = 7, .profile = "MRPHY"},
        {.port_index = 8, .profile = "LL10G"},
        {.port_index = 9, .profile = "TSE PCS"},
        {.port_index = 10, .profile = "TSE MAC"},
        {.port_index = 11, .profile = "Flex-E"},
        {.port_index = 12, .profile = "OTN"},
        {.port_index = 13, .profile = "General PCS-Direct"},
        {.port_index = 14, .profile = "General FEC-Direct"},
        {.port_index = 15, .profile = "General PMA-Direct"},
        {.port_index = 16, .profile = "MII"},
        {.port_index = 17, .profile = "Ethernet PCS-Direct"},
        {.port_index = 18, .profile = "Ethernet FEC-Direct"},
        {.port_index = 19, .profile = "Ethernet PMA-Direct"},
        {.port_index = 20, .profile = "10GbE"},
        {.port_index = 21, .profile = "25GbE"},
        {.port_index = 22, .profile = "40GCAUI-4"},
        {.port_index = 23, .profile = "50GAUI-2"},
        {.port_index = 24, .profile = "50GAUI-1"},
        {.port_index = 25, .profile = "100GAUI-1"},
        {.port_index = 26, .profile = "100GAUI-2"},
        {.port_index = 27, .profile = "100GCAUI-4"},
        {.port_index = 28, .profile = "200GAUI-2"},
        {.port_index = 29, .profile = "200GAUI-4"},
        {.port_index = 30, .profile = "200GAUI-8"},
        {.port_index = 31, .profile = "400GAUI-4"},
        {.port_index = 32, .profile = "400GAUI-8"}
 };


// Parse firmware version
fpga_result parse_fw_ver(char *buf, char *fw_ver, size_t len)
{
        uint32_t  var = 0;
        fpga_result res = FPGA_OK;
        int retval = 0;
        char *endptr = NULL;

        if (buf == NULL || fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        /* BMC FW version format reading
        NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
        NIOS FW is up e.g. 1.0.1 for first release
        [31:24] 8hFF Firmware Support Revision - ASCII code
        0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
        */

        errno = 0;
        var = strtoul(buf, &endptr, 16);
        if (endptr != buf + strlen(buf)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }

        retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);
        if (retval < 0) {
                OPAE_ERR("error in formatting version");
                return FPGA_EXCEPTION;
        }

        return res;
}

// Read BMC firmware version
fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)
{
        fpga_result res = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN] = { 0 };

        if (bmcfw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, bmcfw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}


// Read MAX10 firmware version
fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)
{
        fpga_result res = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN] = { 0 };

        if (max10fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, max10fw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}

// Read mac information
fpga_result read_mac_info(fpga_token token, uint32_t afu_channel_num,
        struct ether_addr *mac_addr)
{
        fpga_result res = FPGA_OK;
        char mac_buf[MACADDR_LEN] = { 0 };
        char mac_count[MACADDR_LEN] = { 0 };
        uint64_t count = 0;
        char *endptr = NULL;

        if (mac_addr == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, mac_buf, MACADDR_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        ether_aton_r(mac_buf, mac_addr);

        res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, mac_count, MACADDR_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        errno = 0;
        count = strtoul(mac_count, &endptr, 16);
        if (endptr != mac_count + strlen(mac_count)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }

        if (afu_channel_num >= count) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        if ((mac_addr->ether_addr_octet[0] == 0xff) &&
                (mac_addr->ether_addr_octet[1] == 0xff) &&
                (mac_addr->ether_addr_octet[2] == 0xff) &&
                (mac_addr->ether_addr_octet[3] == 0xff) &&
                (mac_addr->ether_addr_octet[4] == 0xff) &&
                (mac_addr->ether_addr_octet[5] == 0xff)) {
                OPAE_ERR("Invalid MAC address");
                return FPGA_INVALID_PARAM;
        }

        mac_addr->ether_addr_octet[5] += afu_channel_num;

        return res;
}


// print mac information
fpga_result print_mac_info(fpga_token token)
{
        char mac_str[18] = { 0 };
        struct ether_addr MAC;
        fpga_result res = FPGA_OK;

        memset((void *)&MAC, 0, sizeof(MAC));

        res = read_mac_info(token, 0, &MAC);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read mac address");
        } else {
                printf("%-1s : %s\n", "MAC address",
                        ether_ntoa_r(&MAC, mac_str));
        }

        return res;
}

// print board information
fpga_result print_board_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        fpga_result resval = FPGA_OK;
        char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };
        char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };

        res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read bmc version");
                resval = res;
        }

        res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read max10 version");
                resval = res;
        }

        printf("FPGA SmartNIC N6010 Card \n");
        printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);
        printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);

        return resval;
}




// print phy group information
fpga_result print_phy_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        struct opae_uio uio;
        char feature_dev[SYSFS_MAX_SIZE] = { 0 };
        struct hssi_port_attribute port_profile;
        struct hssi_feature_list  feature_list;
        struct hssi_version  hssi_ver;
        uint8_t *mmap_ptr = NULL;
        uint32_t i = 0;

        res = find_dev_feature(token, HSSI_FEATURE_ID, feature_dev);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to find feature ");
                return res;
        }

        res = opae_uio_open(&uio, feature_dev);
        if (res) {
                OPAE_ERR("Failed to open uio");
                return res;
        }

        res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL);
        if (res) {
                OPAE_ERR("Failed to get uio region");
                opae_uio_close(&uio);
                return res;
        }

        feature_list.csr = *((uint32_t *) (mmap_ptr + HSSI_FEATURE_LIST));
        hssi_ver.csr = *((uint32_t *)(mmap_ptr + HSSI_VERSION));

        printf("//****** HSSI information ******//\n");
        printf("%-32s : %d.%d  \n", "HSSI version", hssi_ver.major, hssi_ver.minor);
        printf("%-32s : %d  \n", "Number of ports", feature_list.hssi_num);

        for (i = 0; i < feature_list.hssi_num; i++) {
                port_profile.csr = *((uint32_t *)(mmap_ptr +
                        HSSI_PORT_ATTRIBUTE + i * 4));

                if (port_profile.profile > HSS_PORT_PROFILE_SIZE) {
                        printf("Port%-28d :%s\n", i, "N/A");
                        continue;
                }

                for (int j = 0; j < HSS_PORT_PROFILE_SIZE; j++) {
                        if (hssi_port_profiles[j].port_index == port_profile.profile) {
                                printf("Port%-28d :%s\n", i, hssi_port_profiles[j].profile);
                                break;
                        }
                 }
        }

        opae_uio_close(&uio);
        return res;
}

// Sec info
fpga_result print_sec_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        fpga_result resval = FPGA_OK;
        fpga_object tcm_object;
        char name[SYSFS_PATH_MAX] = { 0 };

        res = fpgaTokenGetObject(token, DFL_SEC_PMCI_GLOB, &tcm_object,
                FPGA_OBJECT_GLOB);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get token Object");
                return res;
        }
        printf("********** SEC Info START ************ \n");

        // BMC Keys
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_BMC_ROOT, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("BMC root entry hash: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read TCM BMC root entry hash");
                printf("BMC root entry hash: %s\n", "None");
                resval = res;
        }

        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_BMC_CANCEL, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("BMC CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");
        } else {
                OPAE_MSG("Failed to Read BMC CSK IDs canceled");
                printf("BBMC CSK IDs canceled: %s\n", "None");
                resval = res;
        }

        // PR Keys
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_PR_ROOT, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("PR root entry hash: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read PR root entry hash");
                printf("PR root entry hash: %s\n", "None");
                resval = res;
        }

        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_PR_CANCEL, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("AFU/PR CSK IDs canceled: %s\n",
                        strlen(name) > 0 ? name : "None");
        } else {
                OPAE_MSG("Failed to Read AFU CSK/PR IDs canceled");
                printf("AFU/PR CSK IDs canceled: %s\n", "None");
                resval = res;
        }

        // SR Keys
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_SR_ROOT, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("FIM root entry hash: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read FIM root entry hash");
                printf("FIM root entry hash: %s\n", "None");
                resval = res;
        }

        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_SR_CANCEL, name, SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("FIM CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");
        } else {
                OPAE_MSG("Failed to Read FIM CSK IDs canceled");
                printf("FIM CSK IDs canceled: %s\n", "None");
                resval = res;
        }

        // User flash count
        memset(name, 0, sizeof(name));
        res = read_sysfs(token, DFL_SEC_USER_FLASH_COUNT, name,
                SYSFS_PATH_MAX - 1);
        if (res == FPGA_OK) {
                printf("User flash update counter: %s\n", name);
        } else {
                OPAE_MSG("Failed to Read User flash update counter");
                printf("User flash update counter: %s\n", "None");
                resval = res;
        }

        res = fpgaDestroyObject(&tcm_object);
        if (res != FPGA_OK) {
                OPAE_MSG("Failed to Destroy Object");
                resval = res;
        }

        printf("********** SEC Info END ************ \n");

        return resval;
}

// print fme verbose info
fpga_result print_fme_verbose_info(fpga_token token)
{
        UNUSED_PARAM(token);
        return FPGA_OK;;
}

1	// Copyright(c) 2021, Intel Corporation
2	//
3	// Redistribution and use in source and binary forms, with or without
4	// modification, are permitted provided that the following conditions are met:
5	//
6	// * Redistributions of source code must retain the above copyright notice,
7	// this list of conditions and the following disclaimer.
8	// * Redistributions in binary form must reproduce the above copyright notice,
9	// this list of conditions and the following disclaimer in the documentation
10	// and/or other materials provided with the distribution.
11	// * Neither the name of Intel Corporation nor the names of its contributors
12	// may be used to endorse or promote products derived from this software
13	// without specific prior written permission.
14	//
15	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16	// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19	// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20	// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21	// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22	// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23	// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24	// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25	// POSSIBILITY OF SUCH DAMAGE.
26
27	#ifdef HAVE_CONFIG_H
28	#include <config.h>
29	#endif // HAVE_CONFIG_H
30
31	#include <glob.h>
32	#include <stdio.h>
33	#include <errno.h>
34	#include <string.h>
35	#include <opae/properties.h>
36	#include <opae/utils.h>
37	#include <opae/fpga.h>
38	#include <netinet/ether.h>
39	#include <opae/uio.h>
40	#include "../board_common/board_common.h"
41	#include "board_n6010.h"
42
43	#define FPGA_VAR_BUF_LEN 256
44	#define MACADDR_LEN 19
45	#define UNUSED_PARAM(x) ((void)x)
46	#define FEATURE_DEV "/sys/bus/pci/devices/%x:%x:%x.%x/fpga_region"\
47	"/region/dfl-fme/dfl_dev*"
48	// DFL SYSFS
49	#define DFL_SYSFS_BMCFW_VER "dfl*/bmcfw_version"
50	#define DFL_SYSFS_MAX10_VER "dfl*/bmc_version"
51
52	#define DFL_SYSFS_MACADDR_PATH "dfl*/mac_address"
53	#define DFL_SYSFS_MACCNT_PATH "dfl*/mac_count"
54
55	#define DFL_SEC_PMCI_GLOB "dfl/**/security/"
56	#define DFL_SEC_USER_FLASH_COUNT DFL_SEC_PMCI_GLOB "*flash_count"
57	#define DFL_SEC_BMC_CANCEL DFL_SEC_PMCI_GLOB "bmc_canceled_csks"
58	#define DFL_SEC_BMC_ROOT DFL_SEC_PMCI_GLOB "bmc_root_entry_hash"
59	#define DFL_SEC_PR_CANCEL DFL_SEC_PMCI_GLOB "pr_canceled_csks"
60	#define DFL_SEC_PR_ROOT DFL_SEC_PMCI_GLOB "pr_root_entry_hash"
61	#define DFL_SEC_SR_CANCEL DFL_SEC_PMCI_GLOB "sr_canceled_csks"
62	#define DFL_SEC_SR_ROOT DFL_SEC_PMCI_GLOB "sr_root_entry_hash"
63
64
65	#define HSSI_FEATURE_ID 0x15
66	#define HSSI_100G_PROFILE 27
67	#define HSSI_25G_PROFILE 21
68	#define HSSI_10_PROFILE 20
69
70	#define HSSI_FEATURE_LIST 0xC
71	#define HSSI_PORT_ATTRIBUTE 0x10
72	#define HSSI_VERSION 0x8
73	// hssi version
74	struct hssi_version {
75	union {
76	uint32_t csr;
77	struct {
78	uint32_t rsvd : 8;
79	uint32_t minor : 8;
80	uint32_t major : 16;
81	};
82	};
83	};
84
85	// hssi feature list CSR
86	struct hssi_feature_list {
87	union {
88	uint32_t csr;
89	struct {
90	uint32_t axi4_support : 1;
91	uint32_t hssi_num : 4;
92	uint32_t reserved : 27;
93	};
94	};
95	};
96
97	// hssi port attribute CSR
98	//Interface Attribute Port X Parameters, X =0-15
99	//Byte Offset: 0x10 + X * 4
100	struct hssi_port_attribute {
101	union {
102	uint32_t csr;
103	struct {
104	uint32_t profile : 6;
105	uint32_t ready_latency : 4;
106	uint32_t data_bus_width : 3;
107	uint32_t low_speed_mac : 1;
108	uint32_t dynamic_pr : 1;
109	uint32_t reserved : 16;
110	};
111	};
112	};
113
114	typedef struct hssi_port_profile {
115
116	uint32_t port_index;
117	char profile[FPGA_VAR_BUF_LEN];
118
119	} hssi_port_profile;
120
121	#define HSS_PORT_PROFILE_SIZE 33
122
123	hssi_port_profile hssi_port_profiles[] = {
124
125	{.port_index = 0, .profile = "LL100G"},
126	{.port_index = 1, .profile = "Ultra100G"},
127	{.port_index = 2, .profile = "LL50G"},
128	{.port_index = 3, .profile = "LL40G"},
129	{.port_index = 4, .profile = "Ultra40G"},
130	{.port_index = 5, .profile = "25_50G"},
131	{.port_index = 6, .profile = "10_25G"},
132	{.port_index = 7, .profile = "MRPHY"},
133	{.port_index = 8, .profile = "LL10G"},
134	{.port_index = 9, .profile = "TSE PCS"},
135	{.port_index = 10, .profile = "TSE MAC"},
136	{.port_index = 11, .profile = "Flex-E"},
137	{.port_index = 12, .profile = "OTN"},
138	{.port_index = 13, .profile = "General PCS-Direct"},
139	{.port_index = 14, .profile = "General FEC-Direct"},
140	{.port_index = 15, .profile = "General PMA-Direct"},
141	{.port_index = 16, .profile = "MII"},
142	{.port_index = 17, .profile = "Ethernet PCS-Direct"},
143	{.port_index = 18, .profile = "Ethernet FEC-Direct"},
144	{.port_index = 19, .profile = "Ethernet PMA-Direct"},
145	{.port_index = 20, .profile = "10GbE"},
146	{.port_index = 21, .profile = "25GbE"},
147	{.port_index = 22, .profile = "40GCAUI-4"},
148	{.port_index = 23, .profile = "50GAUI-2"},
149	{.port_index = 24, .profile = "50GAUI-1"},
150	{.port_index = 25, .profile = "100GAUI-1"},
151	{.port_index = 26, .profile = "100GAUI-2"},
152	{.port_index = 27, .profile = "100GCAUI-4"},
153	{.port_index = 28, .profile = "200GAUI-2"},
154	{.port_index = 29, .profile = "200GAUI-4"},
155	{.port_index = 30, .profile = "200GAUI-8"},
156	{.port_index = 31, .profile = "400GAUI-4"},
157	{.port_index = 32, .profile = "400GAUI-8"}
158	};
159
160
161	// Parse firmware version
162	fpga_result parse_fw_ver(char buf, char fw_ver, size_t len)	×
163	{
164	uint32_t var = 0;	×
165	fpga_result res = FPGA_OK;	×
166	int retval = 0;	×
167	char *endptr = NULL;	×
168
169	if (buf == NULL \|\| fw_ver == NULL) {	×
170	OPAE_ERR("Invalid Input parameters");	×
171	return FPGA_INVALID_PARAM;	×
172	}
173
174	/* BMC FW version format reading
175	NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
176	NIOS FW is up e.g. 1.0.1 for first release
177	[31:24] 8hFF Firmware Support Revision - ASCII code
178	0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
179	*/
180
181	errno = 0;	×
182	var = strtoul(buf, &endptr, 16);	×
183	if (endptr != buf + strlen(buf)) {	×
184	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	×
185	return FPGA_EXCEPTION;	×
186	}
187
188	retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);	×
189	if (retval < 0) {	×
190	OPAE_ERR("error in formatting version");	×
191	return FPGA_EXCEPTION;	×
192	}
193
194	return res;	×
195	}
196
197	// Read BMC firmware version
198	fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)	2✔
199	{
200	fpga_result res = FPGA_OK;	2✔
201	char buf[FPGA_VAR_BUF_LEN] = { 0 };	2✔
202
203	if (bmcfw_ver == NULL) {	2✔
204	OPAE_ERR("Invalid Input parameters");	×
205	return FPGA_INVALID_PARAM;	×
206	}
207
208	res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);	2✔
209	if (res != FPGA_OK) {	2✔
210	OPAE_ERR("Failed to get read object");	182✔
211	return res;	2✔
212	}
213
214	res = parse_fw_ver(buf, bmcfw_ver, len);	×
215	if (res != FPGA_OK) {	×
216	OPAE_ERR("Failed to parse version ");	×
217	}
218
219	return res;	×
220	}
221
222
223	// Read MAX10 firmware version
224	fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)	2✔
225	{
226	fpga_result res = FPGA_OK;	2✔
227	char buf[FPGA_VAR_BUF_LEN] = { 0 };	2✔
228
229	if (max10fw_ver == NULL) {	2✔
230	OPAE_ERR("Invalid Input parameters");	×
231	return FPGA_INVALID_PARAM;	×
232	}
233
234	res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);	2✔
235	if (res != FPGA_OK) {	2✔
236	OPAE_ERR("Failed to get read object");	182✔
237	return res;	2✔
238	}
239
240	res = parse_fw_ver(buf, max10fw_ver, len);	×
241	if (res != FPGA_OK) {	×
242	OPAE_ERR("Failed to parse version ");	×
243	}
244
245	return res;	×
246	}
247
248	// Read mac information
249	fpga_result read_mac_info(fpga_token token, uint32_t afu_channel_num,	1✔
250	struct ether_addr *mac_addr)
251	{
252	fpga_result res = FPGA_OK;	1✔
253	char mac_buf[MACADDR_LEN] = { 0 };	1✔
254	char mac_count[MACADDR_LEN] = { 0 };	1✔
255	uint64_t count = 0;	1✔
256	char *endptr = NULL;	1✔
257
258	if (mac_addr == NULL) {	1✔
259	OPAE_ERR("Invalid Input parameters");	×
260	return FPGA_INVALID_PARAM;	×
261	}
262
263	res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, mac_buf, MACADDR_LEN - 1);	1✔
264	if (res != FPGA_OK) {	1✔
265	OPAE_ERR("Failed to get read object");	91✔
266	return res;	1✔
267	}
268
269	ether_aton_r(mac_buf, mac_addr);	×
270
271	res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, mac_count, MACADDR_LEN - 1);	×
272	if (res != FPGA_OK) {	×
273	OPAE_ERR("Failed to get read object");	×
274	return res;	×
275	}
276
277	errno = 0;	×
278	count = strtoul(mac_count, &endptr, 16);	×
279	if (endptr != mac_count + strlen(mac_count)) {	×
280	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	×
281	return FPGA_EXCEPTION;	×
282	}
283
284	if (afu_channel_num >= count) {	×
285	OPAE_ERR("Invalid Input parameters");	×
286	return FPGA_INVALID_PARAM;	×
287	}
288
289	if ((mac_addr->ether_addr_octet[0] == 0xff) &&	×
290	(mac_addr->ether_addr_octet[1] == 0xff) &&	×
291	(mac_addr->ether_addr_octet[2] == 0xff) &&	×
292	(mac_addr->ether_addr_octet[3] == 0xff) &&	×
293	(mac_addr->ether_addr_octet[4] == 0xff) &&	×
294	(mac_addr->ether_addr_octet[5] == 0xff)) {	×
295	OPAE_ERR("Invalid MAC address");	×
296	return FPGA_INVALID_PARAM;	×
297	}
298
299	mac_addr->ether_addr_octet[5] += afu_channel_num;	×
300
301	return res;	×
302	}
303
304
305	// print mac information
306	fpga_result print_mac_info(fpga_token token)	1✔
307	{
308	char mac_str[18] = { 0 };	1✔
309	struct ether_addr MAC;
310	fpga_result res = FPGA_OK;	1✔
311
312	memset((void *)&MAC, 0, sizeof(MAC));	1✔
313
314	res = read_mac_info(token, 0, &MAC);	1✔
315	if (res != FPGA_OK) {	1✔
316	OPAE_ERR("Failed to read mac address");	91✔
317	} else {
318	printf("%-1s : %s\n", "MAC address",	×
319	ether_ntoa_r(&MAC, mac_str));
320	}
321
322	return res;	1✔
323	}
324
325	// print board information
326	fpga_result print_board_info(fpga_token token)	1✔
327	{
328	fpga_result res = FPGA_OK;	1✔
329	fpga_result resval = FPGA_OK;	1✔
330	char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };	1✔
331	char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };	1✔
332
333	res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);	1✔
334	if (res != FPGA_OK) {	1✔
335	OPAE_ERR("Failed to read bmc version");	91✔
336	resval = res;	1✔
337	}
338
339	res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);	1✔
340	if (res != FPGA_OK) {	1✔
341	OPAE_ERR("Failed to read max10 version");	91✔
342	resval = res;	1✔
343	}
344
345	printf("FPGA SmartNIC N6010 Card \n");	1✔
346	printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);	1✔
347	printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);	1✔
348
349	return resval;	1✔
350	}
351
352
353
354
355	// print phy group information
356	fpga_result print_phy_info(fpga_token token)	1✔
357	{
358	fpga_result res = FPGA_OK;	1✔
359	struct opae_uio uio;
360	char feature_dev[SYSFS_MAX_SIZE] = { 0 };	1✔
361	struct hssi_port_attribute port_profile;
362	struct hssi_feature_list feature_list;
363	struct hssi_version hssi_ver;
364	uint8_t *mmap_ptr = NULL;	1✔
365	uint32_t i = 0;	1✔
366
367	res = find_dev_feature(token, HSSI_FEATURE_ID, feature_dev);	1✔
368	if (res != FPGA_OK) {	1✔
369	OPAE_ERR("Failed to find feature ");	91✔
370	return res;	1✔
371	}
372
373	res = opae_uio_open(&uio, feature_dev);	×
374	if (res) {	×
375	OPAE_ERR("Failed to open uio");	×
376	return res;	×
377	}
378
379	res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL);	×
380	if (res) {	×
381	OPAE_ERR("Failed to get uio region");	×
382	opae_uio_close(&uio);	×
383	return res;	×
384	}
385
386	feature_list.csr = ((uint32_t ) (mmap_ptr + HSSI_FEATURE_LIST));	×
387	hssi_ver.csr = ((uint32_t )(mmap_ptr + HSSI_VERSION));	×
388
389	printf("//**** HSSI information ****//\n");	×
390	printf("%-32s : %d.%d \n", "HSSI version", hssi_ver.major, hssi_ver.minor);	×
391	printf("%-32s : %d \n", "Number of ports", feature_list.hssi_num);	×
392
393	for (i = 0; i < feature_list.hssi_num; i++) {	×
394	port_profile.csr = ((uint32_t )(mmap_ptr +	×
395	HSSI_PORT_ATTRIBUTE + i * 4));	×
396
397	if (port_profile.profile > HSS_PORT_PROFILE_SIZE) {	×
398	printf("Port%-28d :%s\n", i, "N/A");	×
399	continue;	×
400	}
401
402	for (int j = 0; j < HSS_PORT_PROFILE_SIZE; j++) {	×
403	if (hssi_port_profiles[j].port_index == port_profile.profile) {	×
404	printf("Port%-28d :%s\n", i, hssi_port_profiles[j].profile);	×
405	break;	×
406	}
407	}
408	}
409
410	opae_uio_close(&uio);	×
411	return res;	×
412	}
413
414	// Sec info
415	fpga_result print_sec_info(fpga_token token)	1✔
416	{
417	fpga_result res = FPGA_OK;	1✔
418	fpga_result resval = FPGA_OK;	1✔
419	fpga_object tcm_object;
420	char name[SYSFS_PATH_MAX] = { 0 };	1✔
421
422	res = fpgaTokenGetObject(token, DFL_SEC_PMCI_GLOB, &tcm_object,	1✔
423	FPGA_OBJECT_GLOB);
424	if (res != FPGA_OK) {	1✔
425	OPAE_ERR("Failed to get token Object");	91✔
426	return res;	1✔
427	}
428	printf("******** SEC Info START ********** \n");	×
429
430	// BMC Keys
431	memset(name, 0, sizeof(name));	×
432	res = read_sysfs(token, DFL_SEC_BMC_ROOT, name, SYSFS_PATH_MAX - 1);	×
433	if (res == FPGA_OK) {	×
434	printf("BMC root entry hash: %s\n", name);	×
435	} else {
436	OPAE_MSG("Failed to Read TCM BMC root entry hash");	×
437	printf("BMC root entry hash: %s\n", "None");	×
438	resval = res;	×
439	}
440
441	memset(name, 0, sizeof(name));	×
442	res = read_sysfs(token, DFL_SEC_BMC_CANCEL, name, SYSFS_PATH_MAX - 1);	×
443	if (res == FPGA_OK) {	×
444	printf("BMC CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");	×
445	} else {
446	OPAE_MSG("Failed to Read BMC CSK IDs canceled");	×
447	printf("BBMC CSK IDs canceled: %s\n", "None");	×
448	resval = res;	×
449	}
450
451	// PR Keys
452	memset(name, 0, sizeof(name));	×
453	res = read_sysfs(token, DFL_SEC_PR_ROOT, name, SYSFS_PATH_MAX - 1);	×
454	if (res == FPGA_OK) {	×
455	printf("PR root entry hash: %s\n", name);	×
456	} else {
457	OPAE_MSG("Failed to Read PR root entry hash");	×
458	printf("PR root entry hash: %s\n", "None");	×
459	resval = res;	×
460	}
461
462	memset(name, 0, sizeof(name));	×
463	res = read_sysfs(token, DFL_SEC_PR_CANCEL, name, SYSFS_PATH_MAX - 1);	×
464	if (res == FPGA_OK) {	×
465	printf("AFU/PR CSK IDs canceled: %s\n",	×
466	strlen(name) > 0 ? name : "None");	×
467	} else {
468	OPAE_MSG("Failed to Read AFU CSK/PR IDs canceled");	×
469	printf("AFU/PR CSK IDs canceled: %s\n", "None");	×
470	resval = res;	×
471	}
472
473	// SR Keys
474	memset(name, 0, sizeof(name));	×
475	res = read_sysfs(token, DFL_SEC_SR_ROOT, name, SYSFS_PATH_MAX - 1);	×
476	if (res == FPGA_OK) {	×
477	printf("FIM root entry hash: %s\n", name);	×
478	} else {
479	OPAE_MSG("Failed to Read FIM root entry hash");	×
480	printf("FIM root entry hash: %s\n", "None");	×
481	resval = res;	×
482	}
483
484	memset(name, 0, sizeof(name));	×
485	res = read_sysfs(token, DFL_SEC_SR_CANCEL, name, SYSFS_PATH_MAX - 1);	×
486	if (res == FPGA_OK) {	×
487	printf("FIM CSK IDs canceled: %s\n", strlen(name) > 0 ? name : "None");	×
488	} else {
489	OPAE_MSG("Failed to Read FIM CSK IDs canceled");	×
490	printf("FIM CSK IDs canceled: %s\n", "None");	×
491	resval = res;	×
492	}
493
494	// User flash count
495	memset(name, 0, sizeof(name));	×
496	res = read_sysfs(token, DFL_SEC_USER_FLASH_COUNT, name,	×
497	SYSFS_PATH_MAX - 1);
498	if (res == FPGA_OK) {	×
499	printf("User flash update counter: %s\n", name);	×
500	} else {
501	OPAE_MSG("Failed to Read User flash update counter");	×
502	printf("User flash update counter: %s\n", "None");	×
503	resval = res;	×
504	}
505
506	res = fpgaDestroyObject(&tcm_object);	×
507	if (res != FPGA_OK) {	×
508	OPAE_MSG("Failed to Destroy Object");	×
509	resval = res;	×
510	}
511
512	printf("******** SEC Info END ********** \n");	×
513
514	return resval;	×
515	}
516
517	// print fme verbose info
518	fpga_result print_fme_verbose_info(fpga_token token)	×
519	{
520	UNUSED_PARAM(token);
521	return FPGA_OK;;	×
522	}

OPAE / opae-sdk / 1057057884

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