797932247

Build Type

github

Committed by GitHub

Commit Message

<a href="https://github.com/OPAE/opae-sdk/commit/<a class=hub.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://git"><a class=hub.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://git"><a class=hub.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://git"><a class=hub.com/OPAE/opae-sdk/commit/<a class="double-link" href="https://git"><a class=hub.com/OPAE/opae-sdk/commit/0204e21f7ad61bcbcf27337d148c317d2ce94b1c">0204e21f7">&lt;a href=&quot;https://github.com/OPAE/opae-sdk/commit/</a><a class="double-link" href="https://github.com/OPAE/opae-sdk/commit/&lt;a class=&quot;double-link&quot; href=&quot;https://git">&lt;a class=</a>hub.com/OPAE/opae-sdk/commit/&lt;a class=&quot;double-link&quot; href=&quot;https://git">&lt;a class=</a>hub.com/OPAE/opae-sdk/commit/&lt;a class=&quot;double-link&quot; href=&quot;https://git">&lt;a class=</a>hub.com/OPAE/opae-sdk/commit/0204e21f7ad61bcbcf27337d148c317d2ce94b1c">0204e21f7</a><a href="https://github.com/OPAE/opae-sdk/commit/0204e21f7ad61bcbcf27337d148c317d2ce94b1c">&lt;a href=&quot;https://github.com/OPAE/opae-sdk/commit/0204e21f7ad61bcbcf27337d148c317d2ce94b1c&quot;&gt;&amp;quot;&amp;gt;&amp;amp;lt;a href=&amp;amp;quot;https://github.com/OPAE/opae-sdk/commit/&amp;lt;/a&amp;gt;&amp;lt;a class=&amp;quot;double-link&amp;quot; href=&amp;quot;https://github.com/OPAE/opae-sdk/commit/&amp;amp;lt;a class=&amp;amp;quot;double-link&amp;amp;quot; href=&amp;amp;quot;https://git&amp;quot;&amp;gt;&amp;amp;lt;a class=&amp;lt;/a&amp;gt;hub.com/OPAE/opae-sdk/commit/0204e21f7ad61bcbcf27337d148c317d2ce94b1c&amp;quot;&amp;gt;0204e21f7&amp;lt;/a&amp;gt;&amp;lt;a href=&amp;quot;https://github.com/OPAE/opae-sdk/commit/0204e21f7ad61bcbcf27337d148c317d2ce94b1c&amp;quot;&amp;gt;&amp;amp;lt;a href=&amp;amp;quot;https://github.com/OPAE/opae-sdk/commit/0204e21f7ad61bcbcf27337d148c317d&amp;lt;/a&amp;gt;2</a>ce94b1c&quot;&gt;&amp;quot;&amp;gt;Merge &amp;lt;/a&amp;gt;&amp;lt;a class=&amp;quot;double-link&amp;quot; href=&amp;quot;https://github.com/OPAE/opae-sdk/commit/&amp;lt;a class=&amp;quot;double-link&amp;quot; href=&amp;quot;https://github.com/OPAE/opae-sdk/commit/&lt;a class=&quot;double-link&quot; href=&quot;https://github.com/OPAE/opae-sdk/commit/218ad9a81&quot;&gt;218ad9a81&lt;/a&gt;&lt;a href=&quot;https://github.com/OPAE/opae-sdk/co... (continued)

Pull Request Pull Request #1840: Tools: add fpga smart nic n6010 board module

Run Details

190 of 190 new or added lines in 1 file covered. (100.0%)

10493 of 15911 relevant lines covered (65.95%)

15873.02 hits per line

Source File
Press 'n' to go to next uncovered line, 'b' for previous

43.16

/tools/libboard/board_n6010/board_n6010.c

// Copyright(c) 2021, Intel Corporation
//
// Redistribution  and  use  in source  and  binary  forms,  with  or  without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of  source code  must retain the  above copyright notice,
//   this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
//   this list of conditions and the following disclaimer in the documentation
//   and/or other materials provided with the distribution.
// * Neither the name  of Intel Corporation  nor the names of its contributors
//   may be used to  endorse or promote  products derived  from this  software
//   without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,  BUT NOT LIMITED TO,  THE
// IMPLIED WARRANTIES OF  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED.  IN NO EVENT  SHALL THE COPYRIGHT OWNER  OR CONTRIBUTORS BE
// LIABLE  FOR  ANY  DIRECT,  INDIRECT,  INCIDENTAL,  SPECIAL,  EXEMPLARY,  OR
// CONSEQUENTIAL  DAMAGES  (INCLUDING,  BUT  NOT LIMITED  TO,  PROCUREMENT  OF
// SUBSTITUTE GOODS OR SERVICES;  LOSS OF USE,  DATA, OR PROFITS;  OR BUSINESS
// INTERRUPTION)  HOWEVER CAUSED  AND ON ANY THEORY  OF LIABILITY,  WHETHER IN
// CONTRACT,  STRICT LIABILITY,  OR TORT  (INCLUDING NEGLIGENCE  OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,  EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.

#ifdef HAVE_CONFIG_H
#include <config.h>
#endif // HAVE_CONFIG_H

#include <glob.h>
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <opae/properties.h>
#include <opae/utils.h>
#include <opae/fpga.h>
#include <netinet/ether.h>
#include <opae/uio.h>
#include "../board_common/board_common.h"
#include "board_n6010.h"

#define FPGA_VAR_BUF_LEN       256
#define MACADDR_LEN            19
#define UNUSED_PARAM(x) ((void)x)
#define FEATURE_DEV "/sys/bus/pci/devices/*%x*:*%x*:*%x*.*%x*/fpga_region"\
                                        "/region*/dfl-fme*/dfl_dev*"
// DFL SYSFS
#define DFL_SYSFS_BMCFW_VER                     "dfl*/bmcfw_version"
#define DFL_SYSFS_MAX10_VER                     "dfl*/bmc_version"

#define DFL_SYSFS_MACADDR_PATH                  "dfl*/mac_address"
#define DFL_SYSFS_MACCNT_PATH                   "dfl*/mac_count"

#define HSSI_FEATURE_ID                  0x15
#define HSSI_100G_PROFILE                       27
#define HSSI_25G_PROFILE                        21
#define HSSI_10_PROFILE                         20

#define HSSI_FEATURE_LIST                       0xC
#define HSSI_PORT_ATTRIBUTE                     0x10

// hssi version
struct hssi_version {
        union {
                uint32_t csr;
                struct {
                        uint32_t rsvd : 8;
                        uint32_t minor : 8;
                        uint32_t major : 16;
                };
        };
};

// hssi feature list CSR
struct hssi_feature_list {
        union {
                uint32_t csr;
                struct {
                        uint32_t axi4_support : 1;
                        uint32_t hssi_num : 4;
                        uint32_t reserved : 27;
                };
        };
};

// hssi port attribute CSR
//Interface Attribute Port X Parameters, X =0-15
//Byte Offset: 0x10 + X * 4
struct hssi_port_attribute {
        union {
                uint32_t csr;
                struct {
                        uint32_t profile : 6;
                        uint32_t ready_latency : 4;
                        uint32_t data_bus_width : 3;
                        uint32_t low_speed_mac : 1;
                        uint32_t dynamic_pr : 1;
                        uint32_t reserved : 16;
                };
        };
};


// Parse firmware version
fpga_result parse_fw_ver(char *buf, char *fw_ver, size_t len)
{
        uint32_t  var = 0;
        fpga_result res = FPGA_OK;
        int retval = 0;
        char *endptr = NULL;

        if (buf == NULL || fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        /* BMC FW version format reading
        NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
        NIOS FW is up e.g. 1.0.1 for first release
        [31:24] 8hFF Firmware Support Revision - ASCII code
        0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
        */

        errno = 0;
        var = strtoul(buf, &endptr, 16);
        if (endptr != buf + strlen(buf)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }

        retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);
        if (retval < 0) {
                OPAE_ERR("error in formatting version");
                return FPGA_EXCEPTION;
        }

        return res;
}

// Read BMC firmware version
fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)
{
        fpga_result res = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN] = { 0 };

        if (bmcfw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, bmcfw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}


// Read MAX10 firmware version
fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)
{
        fpga_result res = FPGA_OK;
        char buf[FPGA_VAR_BUF_LEN] = { 0 };

        if (max10fw_ver == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        res = parse_fw_ver(buf, max10fw_ver, len);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to parse version ");
        }

        return res;
}

// Read mac information
fpga_result read_mac_info(fpga_token token, uint32_t afu_channel_num,
        struct ether_addr *mac_addr)
{
        fpga_result res = FPGA_OK;
        char mac_buf[MACADDR_LEN] = { 0 };
        char mac_count[MACADDR_LEN] = { 0 };
        uint64_t count = 0;
        char *endptr = NULL;

        if (mac_addr == NULL) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, mac_buf, MACADDR_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        ether_aton_r(mac_buf, mac_addr);

        res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, mac_count, MACADDR_LEN - 1);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get read object");
                return res;
        }

        errno = 0;
        count = strtoul(mac_count, &endptr, 16);
        if (endptr != mac_count + strlen(mac_count)) {
                OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));
                return FPGA_EXCEPTION;
        }

        if (afu_channel_num >= count) {
                OPAE_ERR("Invalid Input parameters");
                return FPGA_INVALID_PARAM;
        }

        if ((mac_addr->ether_addr_octet[0] == 0xff) &&
                (mac_addr->ether_addr_octet[1] == 0xff) &&
                (mac_addr->ether_addr_octet[2] == 0xff) &&
                (mac_addr->ether_addr_octet[3] == 0xff) &&
                (mac_addr->ether_addr_octet[4] == 0xff) &&
                (mac_addr->ether_addr_octet[5] == 0xff)) {
                OPAE_ERR("Invalid MAC address");
                return FPGA_INVALID_PARAM;
        }

        mac_addr->ether_addr_octet[5] += afu_channel_num;

        return res;
}


// print mac information
fpga_result print_mac_info(fpga_token token)
{
        char mac_str[18] = { 0 };
        struct ether_addr MAC;
        fpga_result res = FPGA_OK;

        memset((void *)&MAC, 0, sizeof(MAC));

        res = read_mac_info(token, 0, &MAC);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read mac address");
        } else {
                printf("%-1s : %s\n", "MAC address",
                        ether_ntoa_r(&MAC, mac_str));
        }

        return res;
}

// print board information
fpga_result print_board_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        fpga_result resval = FPGA_OK;
        char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };
        char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };

        res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read bmc version");
                resval = res;
        }

        res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to read max10 version");
                resval = res;
        }

        printf("FPGA SmartNIC N6010 Card \n");
        printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);
        printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);

        return resval;
}

// enumerate hssi feature 0x15
fpga_result enum_hssi_feature(fpga_token token,
                char *feature_dev)
{
        fpga_result res                 = FPGA_OK;
        char sysfs_path[SYSFS_MAX_SIZE] = { 0 };
        uint8_t bus                     = (uint8_t)-1;
        uint16_t segment                = (uint16_t)-1;
        uint8_t device                  = (uint8_t)-1;
        uint8_t function                = (uint8_t)-1;
        size_t i                        = 0;
        uint64_t value                  = 0;
        int gres                        = 0;
        glob_t pglob;

        res = get_fpga_sbdf(token, &segment, &bus, &device, &function);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get sbdf ");
                return res;
        }

        if (snprintf(sysfs_path, sizeof(sysfs_path),
                FEATURE_DEV,
                segment, bus, device, function) < 0) {
                OPAE_ERR("snprintf buffer overflow");
                return FPGA_EXCEPTION;
        }

        gres = glob(sysfs_path, GLOB_NOSORT, NULL, &pglob);
        if (gres) {
                OPAE_ERR("Failed pattern match %s: %s", sysfs_path, strerror(errno));
                globfree(&pglob);
                return FPGA_NOT_FOUND;
        }

        if (pglob.gl_pathc >= 1) {
                OPAE_ERR("gl_pathc = 1");
                memset(sysfs_path, 0, sizeof(sysfs_path));
                if (snprintf(sysfs_path, sizeof(sysfs_path),
                        "%s/feature_id", pglob.gl_pathv[0]) < 0) {
                        OPAE_ERR("snprintf buffer overflow");
                        res = FPGA_EXCEPTION;
                        goto out;
                }

                res = sysfs_read_u64(sysfs_path, &value);
                if (res != FPGA_OK) {
                        OPAE_MSG("Failed to read sysfs value");
                        goto out;
                }

                if (value == HSSI_FEATURE_ID) {
                        char *p = strstr(pglob.gl_pathv[i], "dfl_dev");
                        if (p == NULL) {
                                res = FPGA_NOT_FOUND;
                                goto out;
                        }

                        if (snprintf(feature_dev, SYSFS_MAX_SIZE,
                                "%s", p) < 0) {
                                OPAE_ERR("snprintf buffer overflow");
                                res = FPGA_EXCEPTION;
                                goto out;
                        }
                }
        } else {
                res = FPGA_NOT_FOUND;
                goto out;
        }


out:
        globfree(&pglob);
        return res;
}

// print phy group information
fpga_result print_phy_info(fpga_token token)
{
        fpga_result res = FPGA_OK;
        struct opae_uio uio;
        char feature_dev[SYSFS_MAX_SIZE] = { 0 };
        struct hssi_port_attribute port_profile;
        struct hssi_feature_list  feature_list;
        uint8_t *mmap_ptr = NULL;
        uint32_t *_ptr = NULL;
        uint32_t i = 0;

        res = enum_hssi_feature(token, feature_dev);
        if (res != FPGA_OK) {
                OPAE_ERR("Failed to get hssi feature");
                return res;
        }
        res = opae_uio_open(&uio, feature_dev);
        if (res) {
                OPAE_ERR("Failed to open uio");
                return res;
        }

        res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL);
        if (res) {
                OPAE_ERR("Failed to get uio region");
                return res;
        }
        _ptr = (uint32_t *)mmap_ptr;
        feature_list.csr = *(_ptr + HSSI_FEATURE_LIST);
        for (i = 0; i < feature_list.hssi_num; i++) {
                port_profile.csr = *(_ptr + HSSI_PORT_ATTRIBUTE + i);

                if (port_profile.profile == HSSI_100G_PROFILE) {
                        printf("Port%d : %s \n", i, "100GCAUI-4");
                } else if (port_profile.profile == HSSI_25G_PROFILE) {
                        printf("Port%d : %s \n", i, "25GbE");
                } else if (port_profile.profile == HSSI_10_PROFILE) {
                        printf("Port%d : %s \n", i, "10GbE");
                } else {
                        printf("Invalid port ");
                }
        }

        return res;
}

// Sec info
fpga_result print_sec_info(fpga_token token)
{
        return print_sec_common_info(token);
}

// print fme verbose info
fpga_result print_fme_verbose_info(fpga_token token)
{
        UNUSED_PARAM(token);
        return FPGA_OK;;
}

1	// Copyright(c) 2021, Intel Corporation
2	//
3	// Redistribution and use in source and binary forms, with or without
4	// modification, are permitted provided that the following conditions are met:
5	//
6	// * Redistributions of source code must retain the above copyright notice,
7	// this list of conditions and the following disclaimer.
8	// * Redistributions in binary form must reproduce the above copyright notice,
9	// this list of conditions and the following disclaimer in the documentation
10	// and/or other materials provided with the distribution.
11	// * Neither the name of Intel Corporation nor the names of its contributors
12	// may be used to endorse or promote products derived from this software
13	// without specific prior written permission.
14	//
15	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16	// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19	// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20	// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21	// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22	// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23	// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24	// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25	// POSSIBILITY OF SUCH DAMAGE.
26
27	#ifdef HAVE_CONFIG_H
28	#include <config.h>
29	#endif // HAVE_CONFIG_H
30
31	#include <glob.h>
32	#include <stdio.h>
33	#include <errno.h>
34	#include <string.h>
35	#include <opae/properties.h>
36	#include <opae/utils.h>
37	#include <opae/fpga.h>
38	#include <netinet/ether.h>
39	#include <opae/uio.h>
40	#include "../board_common/board_common.h"
41	#include "board_n6010.h"
42
43	#define FPGA_VAR_BUF_LEN 256
44	#define MACADDR_LEN 19
45	#define UNUSED_PARAM(x) ((void)x)
46	#define FEATURE_DEV "/sys/bus/pci/devices/%x:%x:%x.%x/fpga_region"\
47	"/region/dfl-fme/dfl_dev*"
48	// DFL SYSFS
49	#define DFL_SYSFS_BMCFW_VER "dfl*/bmcfw_version"
50	#define DFL_SYSFS_MAX10_VER "dfl*/bmc_version"
51
52	#define DFL_SYSFS_MACADDR_PATH "dfl*/mac_address"
53	#define DFL_SYSFS_MACCNT_PATH "dfl*/mac_count"
54
55	#define HSSI_FEATURE_ID 0x15
56	#define HSSI_100G_PROFILE 27
57	#define HSSI_25G_PROFILE 21
58	#define HSSI_10_PROFILE 20
59
60	#define HSSI_FEATURE_LIST 0xC
61	#define HSSI_PORT_ATTRIBUTE 0x10
62
63	// hssi version
64	struct hssi_version {
65	union {
66	uint32_t csr;
67	struct {
68	uint32_t rsvd : 8;
69	uint32_t minor : 8;
70	uint32_t major : 16;
71	};
72	};
73	};
74
75	// hssi feature list CSR
76	struct hssi_feature_list {
77	union {
78	uint32_t csr;
79	struct {
80	uint32_t axi4_support : 1;
81	uint32_t hssi_num : 4;
82	uint32_t reserved : 27;
83	};
84	};
85	};
86
87	// hssi port attribute CSR
88	//Interface Attribute Port X Parameters, X =0-15
89	//Byte Offset: 0x10 + X * 4
90	struct hssi_port_attribute {
91	union {
92	uint32_t csr;
93	struct {
94	uint32_t profile : 6;
95	uint32_t ready_latency : 4;
96	uint32_t data_bus_width : 3;
97	uint32_t low_speed_mac : 1;
98	uint32_t dynamic_pr : 1;
99	uint32_t reserved : 16;
100	};
101	};
102	};
103
104
105	// Parse firmware version
106	fpga_result parse_fw_ver(char buf, char fw_ver, size_t len)	×
107	{
108	uint32_t var = 0;	×
109	fpga_result res = FPGA_OK;	×
110	int retval = 0;	×
111	char *endptr = NULL;	×
112
113	if (buf == NULL \|\| fw_ver == NULL) {	×
114	OPAE_ERR("Invalid Input parameters");	×
115	return FPGA_INVALID_PARAM;	×
116	}
117
118	/* BMC FW version format reading
119	NIOS II Firmware Build 0x0 32 RW[23:0] 24 hFFFFFF Build version of NIOS II Firmware
120	NIOS FW is up e.g. 1.0.1 for first release
121	[31:24] 8hFF Firmware Support Revision - ASCII code
122	0xFF is the default value without NIOS FW, will be changed after NIOS FW is up
123	*/
124
125	errno = 0;	×
126	var = strtoul(buf, &endptr, 16);	×
127	if (endptr != buf + strlen(buf)) {	×
128	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	×
129	return FPGA_EXCEPTION;	×
130	}
131
132	retval = snprintf(fw_ver, len, "%u.%u.%u", (var >> 16) & 0xff, (var >> 8) & 0xff, var & 0xff);	×
133	if (retval < 0) {	×
134	OPAE_ERR("error in formatting version");	×
135	return FPGA_EXCEPTION;	×
136	}
137
138	return res;	×
139	}
140
141	// Read BMC firmware version
142	fpga_result read_bmcfw_version(fpga_token token, char *bmcfw_ver, size_t len)	2✔
143	{
144	fpga_result res = FPGA_OK;	2✔
145	char buf[FPGA_VAR_BUF_LEN] = { 0 };	2✔
146
147	if (bmcfw_ver == NULL) {	2✔
148	OPAE_ERR("Invalid Input parameters");	×
149	return FPGA_INVALID_PARAM;	×
150	}
151
152	res = read_sysfs(token, DFL_SYSFS_BMCFW_VER, buf, FPGA_VAR_BUF_LEN - 1);	2✔
153	if (res != FPGA_OK) {	2✔
154	OPAE_ERR("Failed to get read object");	182✔
155	return res;	2✔
156	}
157
158	res = parse_fw_ver(buf, bmcfw_ver, len);	×
159	if (res != FPGA_OK) {	×
160	OPAE_ERR("Failed to parse version ");	×
161	}
162
163	return res;	×
164	}
165
166
167	// Read MAX10 firmware version
168	fpga_result read_max10fw_version(fpga_token token, char *max10fw_ver, size_t len)	2✔
169	{
170	fpga_result res = FPGA_OK;	2✔
171	char buf[FPGA_VAR_BUF_LEN] = { 0 };	2✔
172
173	if (max10fw_ver == NULL) {	2✔
174	OPAE_ERR("Invalid Input parameters");	×
175	return FPGA_INVALID_PARAM;	×
176	}
177
178	res = read_sysfs(token, DFL_SYSFS_MAX10_VER, buf, FPGA_VAR_BUF_LEN - 1);	2✔
179	if (res != FPGA_OK) {	2✔
180	OPAE_ERR("Failed to get read object");	182✔
181	return res;	2✔
182	}
183
184	res = parse_fw_ver(buf, max10fw_ver, len);	×
185	if (res != FPGA_OK) {	×
186	OPAE_ERR("Failed to parse version ");	×
187	}
188
189	return res;	×
190	}
191
192	// Read mac information
193	fpga_result read_mac_info(fpga_token token, uint32_t afu_channel_num,	1✔
194	struct ether_addr *mac_addr)
195	{
196	fpga_result res = FPGA_OK;	1✔
197	char mac_buf[MACADDR_LEN] = { 0 };	1✔
198	char mac_count[MACADDR_LEN] = { 0 };	1✔
199	uint64_t count = 0;	1✔
200	char *endptr = NULL;	1✔
201
202	if (mac_addr == NULL) {	1✔
203	OPAE_ERR("Invalid Input parameters");	×
204	return FPGA_INVALID_PARAM;	×
205	}
206
207	res = read_sysfs(token, DFL_SYSFS_MACADDR_PATH, mac_buf, MACADDR_LEN - 1);	1✔
208	if (res != FPGA_OK) {	1✔
209	OPAE_ERR("Failed to get read object");	91✔
210	return res;	1✔
211	}
212
213	ether_aton_r(mac_buf, mac_addr);	×
214
215	res = read_sysfs(token, DFL_SYSFS_MACCNT_PATH, mac_count, MACADDR_LEN - 1);	×
216	if (res != FPGA_OK) {	×
217	OPAE_ERR("Failed to get read object");	×
218	return res;	×
219	}
220
221	errno = 0;	×
222	count = strtoul(mac_count, &endptr, 16);	×
223	if (endptr != mac_count + strlen(mac_count)) {	×
224	OPAE_ERR("Failed to convert buffer to integer: %s", strerror(errno));	×
225	return FPGA_EXCEPTION;	×
226	}
227
228	if (afu_channel_num >= count) {	×
229	OPAE_ERR("Invalid Input parameters");	×
230	return FPGA_INVALID_PARAM;	×
231	}
232
233	if ((mac_addr->ether_addr_octet[0] == 0xff) &&	×
234	(mac_addr->ether_addr_octet[1] == 0xff) &&	×
235	(mac_addr->ether_addr_octet[2] == 0xff) &&	×
236	(mac_addr->ether_addr_octet[3] == 0xff) &&	×
237	(mac_addr->ether_addr_octet[4] == 0xff) &&	×
238	(mac_addr->ether_addr_octet[5] == 0xff)) {	×
239	OPAE_ERR("Invalid MAC address");	×
240	return FPGA_INVALID_PARAM;	×
241	}
242
243	mac_addr->ether_addr_octet[5] += afu_channel_num;	×
244
245	return res;	×
246	}
247
248
249	// print mac information
250	fpga_result print_mac_info(fpga_token token)	1✔
251	{
252	char mac_str[18] = { 0 };	1✔
253	struct ether_addr MAC;
254	fpga_result res = FPGA_OK;	1✔
255
256	memset((void *)&MAC, 0, sizeof(MAC));	1✔
257
258	res = read_mac_info(token, 0, &MAC);	1✔
259	if (res != FPGA_OK) {	1✔
260	OPAE_ERR("Failed to read mac address");	91✔
261	} else {
262	printf("%-1s : %s\n", "MAC address",	×
263	ether_ntoa_r(&MAC, mac_str));
264	}
265
266	return res;	1✔
267	}
268
269	// print board information
270	fpga_result print_board_info(fpga_token token)	1✔
271	{
272	fpga_result res = FPGA_OK;	1✔
273	fpga_result resval = FPGA_OK;	1✔
274	char bmc_ver[FPGA_VAR_BUF_LEN] = { 0 };	1✔
275	char max10_ver[FPGA_VAR_BUF_LEN] = { 0 };	1✔
276
277	res = read_bmcfw_version(token, bmc_ver, FPGA_VAR_BUF_LEN);	1✔
278	if (res != FPGA_OK) {	1✔
279	OPAE_ERR("Failed to read bmc version");	91✔
280	resval = res;	1✔
281	}
282
283	res = read_max10fw_version(token, max10_ver, FPGA_VAR_BUF_LEN);	1✔
284	if (res != FPGA_OK) {	1✔
285	OPAE_ERR("Failed to read max10 version");	91✔
286	resval = res;	1✔
287	}
288
289	printf("FPGA SmartNIC N6010 Card \n");	1✔
290	printf("Board Management Controller, MAX10 NIOS FW version: %s \n", bmc_ver);	1✔
291	printf("Board Management Controller, MAX10 Build version: %s \n", max10_ver);	1✔
292
293	return resval;	1✔
294	}
295
296	// enumerate hssi feature 0x15
297	fpga_result enum_hssi_feature(fpga_token token,	2✔
298	char *feature_dev)
299	{
300	fpga_result res = FPGA_OK;	2✔
301	char sysfs_path[SYSFS_MAX_SIZE] = { 0 };	2✔
302	uint8_t bus = (uint8_t)-1;	2✔
303	uint16_t segment = (uint16_t)-1;	2✔
304	uint8_t device = (uint8_t)-1;	2✔
305	uint8_t function = (uint8_t)-1;	2✔
306	size_t i = 0;	2✔
307	uint64_t value = 0;	2✔
308	int gres = 0;	2✔
309	glob_t pglob;
310
311	res = get_fpga_sbdf(token, &segment, &bus, &device, &function);	2✔
312	if (res != FPGA_OK) {	2✔
313	OPAE_ERR("Failed to get sbdf ");	×
314	return res;	×
315	}
316
317	if (snprintf(sysfs_path, sizeof(sysfs_path),	2✔
318	FEATURE_DEV,
319	segment, bus, device, function) < 0) {
320	OPAE_ERR("snprintf buffer overflow");	×
321	return FPGA_EXCEPTION;	×
322	}
323
324	gres = glob(sysfs_path, GLOB_NOSORT, NULL, &pglob);	2✔
325	if (gres) {	2✔
326	OPAE_ERR("Failed pattern match %s: %s", sysfs_path, strerror(errno));	182✔
327	globfree(&pglob);	2✔
328	return FPGA_NOT_FOUND;	2✔
329	}
330
331	if (pglob.gl_pathc >= 1) {	×
332	OPAE_ERR("gl_pathc = 1");	×
333	memset(sysfs_path, 0, sizeof(sysfs_path));	×
334	if (snprintf(sysfs_path, sizeof(sysfs_path),	×
335	"%s/feature_id", pglob.gl_pathv[0]) < 0) {	×
336	OPAE_ERR("snprintf buffer overflow");	×
337	res = FPGA_EXCEPTION;	×
338	goto out;	×
339	}
340
341	res = sysfs_read_u64(sysfs_path, &value);	×
342	if (res != FPGA_OK) {	×
343	OPAE_MSG("Failed to read sysfs value");	×
344	goto out;	×
345	}
346
347	if (value == HSSI_FEATURE_ID) {	×
348	char *p = strstr(pglob.gl_pathv[i], "dfl_dev");	×
349	if (p == NULL) {	×
350	res = FPGA_NOT_FOUND;	×
351	goto out;	×
352	}
353
354	if (snprintf(feature_dev, SYSFS_MAX_SIZE,	×
355	"%s", p) < 0) {
356	OPAE_ERR("snprintf buffer overflow");	×
357	res = FPGA_EXCEPTION;	×
358	goto out;	×
359	}
360	}
361	} else {
362	res = FPGA_NOT_FOUND;	×
363	goto out;	×
364	}
365
366
367	out:	×
368	globfree(&pglob);	×
369	return res;	×
370	}
371
372	// print phy group information
373	fpga_result print_phy_info(fpga_token token)	1✔
374	{
375	fpga_result res = FPGA_OK;	1✔
376	struct opae_uio uio;
377	char feature_dev[SYSFS_MAX_SIZE] = { 0 };	1✔
378	struct hssi_port_attribute port_profile;
379	struct hssi_feature_list feature_list;
380	uint8_t *mmap_ptr = NULL;	1✔
381	uint32_t *_ptr = NULL;	1✔
382	uint32_t i = 0;	1✔
383
384	res = enum_hssi_feature(token, feature_dev);	1✔
385	if (res != FPGA_OK) {	1✔
386	OPAE_ERR("Failed to get hssi feature");	91✔
387	return res;	1✔
388	}
389	res = opae_uio_open(&uio, feature_dev);	×
390	if (res) {	×
391	OPAE_ERR("Failed to open uio");	×
392	return res;	×
393	}
394
395	res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL);	×
396	if (res) {	×
397	OPAE_ERR("Failed to get uio region");	×
398	return res;	×
399	}
400	_ptr = (uint32_t *)mmap_ptr;	×
401	feature_list.csr = *(_ptr + HSSI_FEATURE_LIST);	×
402	for (i = 0; i < feature_list.hssi_num; i++) {	×
403	port_profile.csr = *(_ptr + HSSI_PORT_ATTRIBUTE + i);	×
404
405	if (port_profile.profile == HSSI_100G_PROFILE) {	×
406	printf("Port%d : %s \n", i, "100GCAUI-4");	×
407	} else if (port_profile.profile == HSSI_25G_PROFILE) {	×
408	printf("Port%d : %s \n", i, "25GbE");	×
409	} else if (port_profile.profile == HSSI_10_PROFILE) {	×
410	printf("Port%d : %s \n", i, "10GbE");	×
411	} else {
412	printf("Invalid port ");	×
413	}
414	}
415
416	return res;	×
417	}
418
419	// Sec info
420	fpga_result print_sec_info(fpga_token token)	1✔
421	{
422	return print_sec_common_info(token);	1✔
423	}
424
425	// print fme verbose info
426	fpga_result print_fme_verbose_info(fpga_token token)	×
427	{
428	UNUSED_PARAM(token);
429	return FPGA_OK;;	×
430	}

OPAE / opae-sdk / 797932247

Source File Press 'n' to go to next uncovered line, 'b' for previous

Source File
Press 'n' to go to next uncovered line, 'b' for previous