• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

nickg / nvc / 13798777898 / 1
92%
master: 92%

Build:
DEFAULT BRANCH: master
Ran 11 Mar 2025 09:50PM UTC
Files 91
Run time 6s
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

11 Mar 2025 08:20PM UTC coverage: 92.333% (+0.02%) from 92.318%
13798777898.1

push

github

nickg
Implement __FILE__ and __LINE__ in Verilog preprocessor

68139 of 73797 relevant lines covered (92.33%)

432233.27 hits per line

Source Files on job 13798777898.1
  • Tree
  • List 91
  • Changed 4
  • Source Changed 0
  • Coverage Changed 4
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Build 13798777898
  • 3148e826 on github
  • Prev Job for on master (#13775379932.1)
  • Next Job for on master (#13821806931.1)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2025 Coveralls, Inc